Collaborative Research: Enabling Technology for On-Chip Networks

摘要半导体技术和计算机系统的发展使得互连网络，特别是片上互连网络（ocn）成为一项关键技术。近年来，单处理器的性能已经达到了一个平台，导致处理器制造商在一个芯片上组合了许多处理器。这种多核或多核芯片多处理器（CMP）体系结构依赖于OCN来提供处理器、缓存存储器模块、外部存储器和I/O设备之间的通信。在这样的系统中，很大一部分面积和功率被通信消耗，这使得ocn更加关键。pi建议为ocn开发使能技术（电路和架构）。他们将开发电路，预计可将OCN功率降低10倍，并将性能不变的OCN成本降低4倍。这种电路级的工作将能够为关键OCN组件的成本、功率和性能开发准确的模型。使用这些模型，新的网络架构将被开发出来，有望将OCN和理想互连之间的差距缩小到目前尺寸的三分之一。开发的技术将通过实现优化的OCN来演示完成布局的水平。虽然OCN将以CMP为目标，并通过RAMP基础设施由CMP工作负载驱动，但pi也将与片上系统团队合作，将拟议的电路宏和架构设计注入其设计工具链。

Project AbstractThe evolution of semiconductor technology and computer systems has made interconnection networks, and particularly on-chip interconnection networks (OCNs), a critical technology. In recent years, single-processor performance has reached a plateau, leading processor manufacturers to combine many processors on a chip. Such multi-core or many-core chip multi-processor (CMP) architectures depend on an OCN to provide communication between processors, cache memory modules, and external memories and I/O devices. A large fraction of area and power in such systems is consumed by communication making OCNs even more critical.The PIs propose to develop enabling technology (circuits and architecture) for OCNs. They will develop circuits that are expected to reduce OCN power by 10x and decrease cost by 4x for an OCN with constant performance. This circuit-level work will enable the development of accurate models for the cost, power, and performance for key OCN components. Using these models, new network architectures will be developed that are expected to close much of the gap between an OCN and the ideal interconnect to 1/3 of its present size. The technology developed will be demonstrated through implementing an optimized OCN to the level of completed layout. While the OCN will be targeted for CMPs and driven by CMP workloads through the RAMP infrastructure, the PIs will also be working with systems-on-chip groups to inject the proposed circuit macros and architectural designs into their design tool-chains.