Collaborative Research: Enabling Technology for On-Chip Networks

合作研究：片上网络的支持技术

• 批准号: 0702110
• 负责人: Li-Shiuan Peh
• 金额: $ 27.5万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-06-01 至 2010-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702110&HistoricalAwards=false
• 关键词: Collaborative; Research; Enabling; Technology; Chip

Project AbstractThe evolution of semiconductor technology and computer systems has made interconnection networks, and particularly on-chip interconnection networks (OCNs), a critical technology. In recent years, single-processor performance has reached a plateau, leading processor manufacturers to combine many processors on a chip. Such multi-core or many-core chip multi-processor (CMP) architectures depend on an OCN to provide communication between processors, cache memory modules, and external memories and I/O devices. A large fraction of area and power in such systems is consumed by communication making OCNs even more critical.The PIs propose to develop enabling technology (circuits and architecture) for OCNs. They will develop circuits that are expected to reduce OCN power by 10x and decrease cost by 4x for an OCN with constant performance. This circuit-level work will enable the development of accurate models for the cost, power, and performance for key OCN components. Using these models, new network architectures will be developed that are expected to close much of the gap between an OCN and the ideal interconnect to 1/3 of its present size. The technology developed will be demonstrated through implementing an optimized OCN to the level of completed layout. While the OCN will be targeted for CMPs and driven by CMP workloads through the RAMP infrastructure, the PIs will also be working with systems-on-chip groups to inject the proposed circuit macros and architectural designs into their design tool-chains.

半导体技术和计算机系统的发展使得互连网络，特别是片上互连网络（OCN）成为一项关键技术。近年来，单处理器性能已达到稳定水平，导致处理器制造商将联合收割机许多处理器组合在一个芯片上。这种多核或众核芯片多处理器（CMP）架构依赖于OCN来提供处理器、高速缓存存储器模块和外部存储器与I/O设备之间的通信。 在这样的系统中，很大一部分面积和功率被通信消耗，使得OCN变得更加关键。PI建议为OCN开发使能技术（电路和架构）。他们将开发电路，预计将OCN功耗降低10倍，成本降低4倍，使OCN具有恒定的性能。这种电路级的工作将能够为关键OCN组件的成本、功耗和性能开发精确的模型。使用这些模型，将开发新的网络体系结构，预计将关闭OCN和理想互连之间的差距的1/3，其目前的大小。开发的技术将通过实施优化的OCN到完成布局的水平来展示。虽然OCN将针对CMP，并通过RAMP基础设施由CMP工作负载驱动，但PI也将与片上系统团队合作，将拟议的电路宏和架构设计注入其设计工具链。