Collaborative Research: CPA-CSA: CMP Architectures with Global Communication

本提案的重点是评估在大规模芯片多处理器（cmp）中使用瞬时的、芯片范围内的全局信息来提高性能、降低功耗和成本。使用全局信息与传统思维相矛盾，因为人们一直认为遍历整个芯片需要许多时钟周期。然而，最近开发的电路可以实现单周期、芯片范围的信号传输，这表明同时结合全球和本地信息的新可能性。此外，由于设计灵活性、互连可配置性和晶体管性能的改进只存在于芯片上，类似的想法以前没有在大型传统多芯片系统中实现。初步探索已经确定了所需的互连电路和硬件和软件利用最新全球信息的机会。该研究计划开发新的电路技术，以实现拟议的带有混合互连（NOCHI）架构的片上网络（NOC），该架构既具有使用传统互连技术的数据平面，又具有具有全局互连的超低延迟控制平面。由于NOCHI忽略了已建立的设计模式，因此了解电路特性对于架构研究至关重要，其中包括：可以更好地控制和调节网络内和核间功耗的新算法；改进了内核与片外存储系统的交互，减少了对片上网络资源的需求；全球信息对缓存一致性和管理的影响；软件控制，超低延迟的高效多核同步。

The focus of this proposal is to evaluate the use of instantaneous, chip-wide global information for increasing performance and reducing power and cost in large-scale, chip multi-processors (CMPs). Using global information contradicts conventional thinking because it has been assumed that traversing the entire chip requires many clock periods. Recently developed circuits, however, enable single-cycle, chip-wide signaling, suggesting new possibilities of combining global and local information simultaneously. Further, similar ideas have not been previously implemented in large, traditional multi-chip systems because design flexibility, interconnect configurability, and transistor performance improvements exist only on chip. Preliminary exploration has identified both the required interconnect circuits and opportunities for hardware and software to take advantage of up-to-date global information. The research plans to exploit new circuit techniques that will enable the proposed network-on-chip (NOC)with hybrid interconnect (NOCHI) architecture, which has both a data plane using conventional interconnect techniques and an ultra low-latency control plane with a global interconnect. Because NOCHI ignores established design patterns, understanding the circuit properties is essential for the architectural studies, which include: new algorithms that can better control and regulate power consumption within the network and across cores; improved interaction of the cores with the off-chip memory system to reduce demands on on-chip network resources; the ramifications of global information on cache coherence and management; and software controlled, ultra low-latency efficient synchronization for multicores.