Architectures and Applications for Three-Dimensional Chip Multiprocessors

该项目研究多核架构、先进的设计工具和高度并行的应用，以开发三维集成电路(3D IC)，与传统的二维多核芯片相比，可显著提高性能和降低功耗。我们的目标是利用这两个维度并将其扩展到下一个计算前沿：每秒万亿次运算(TeraOPS)的性能，功耗低于10W。该项目涉及对各种体系结构替代方案的详细权衡分析，特别是关于存储器层次和互连网络，以发现充分利用3D集成的好处的方法。这种分析将在体系结构级别和物理设计级别进行，并将开发工具，以允许信息和约束在这些抽象级别之间顺利流动，从而为架构师和芯片设计者之间的合作创造新的机会。

This project investigates multicore architectures, advanced design tools, and highly-parallel applications to exploit three-dimensional integrated circuits (3D ICs) for significantly higher performance and reduced power, compared to traditional two-dimensional multicore chips. The goal is to exploit and extend both dimensions into the next computational frontier: trillion Operations-per-Second (TeraOPS) performance with less than 10W of power dissipation. The project involves detailed tradeoff analyses of architectural alternatives, especially with respect to memory hierarchy and interconnection networks, in order to discover approaches that fully exploit the benefits of 3D integration. This analysis will be performed at both the architectural level and the physical design level, and tools will be developed to allow information and constraints to smoothly flow between these levels of abstraction, enabling new opportunities for collaboration between architects and chip designers.