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Sequentially Transparent Synthesis

Sequentially Transparent Synthesis
顺序透明合成
批准号:
0702668
负责人:
Robert Brayton
金额:
$0.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2007
资助国家:
美国
项目状态:
已结题
起止时间:
2007-07-01 至 2010-06-30

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英文摘要
ID: CCF-0702668Project Title: Sequentially Transparent SynthesisPI name: Brayton, Robert K. Institution: University of California-BerkeleyAbstract:Microelectronic devices are already pervasive in our everyday life, from computers to video games. Efficient manufacturing of these devices is key to this country's technology competitiveness and implies automating the design process. Thus, computer-aided design (CAD) software, capable of representing, optimizing, and implementing complex digital systems needs to be researched and continually developed. This is a demanding task and without continual research, development of CAD software will not keep up with the growing demands on the capacity, variety, and speed of designing new digital electronic systems.The proposed work focuses on basic research in the key area of automatically creating and transforming functional descriptions of electronic systems that are being designed. The goal is optimization, targeting criteria that vary depending on the design needs, e.g. optimizing for minimal power consumption, which is important for portable devices, such as cell phones, as well the huge banks of compute servers that power the internet. A primary focus of this research is in an area called sequential synthesis and verification. Most digital systems can be viewed abstractly as finite state machines (FSMs). Most CAD algorithms, which optimize these, work on a very limited view of FSMs by ignoring the memory components (called combinational optimization). This leads to very suboptimal results. Optimizations, which manipulate the memory (sequential optimization) are usually ignored because they are not scalable to large systems, and it is too hard to verify the correctness of the result. The research to be performed (1) advocates a novel representation of FSM functionality that makes sequential optimization and validation easier and (2) unifies several previously unrelated optimization goals, which allows for finding better solutions in shorter time.The project, when successfully completed, will contribute to the research and development of a new generation of efficient CAD software. It will boost designer productivity, lower development costs, and shorten the time to market for the design, implementation, and verification of complex systems.
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SHF: Small: Bit-level Formal Verification: Keeping Pace with Industrial Needs
  • 批准号:
    1219154
  • 项目类别:
    Standard Grant
  • 资助金额:
    $45.0万
  • 财政年份:
    2012
  • 负责人:
    Robert Brayton
  • 依托单位:
ITR: Synthesis System for Discrete Event Systems through Solving Equations over Mathematical Machines
  • 批准号:
    0312676
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $30.0万
  • 财政年份:
    2003
  • 负责人:
    Robert Brayton
  • 依托单位:
海外基金