NER: Modeling and Design of Nanotube-Based On-Chip Interconnect Solutions for Future VLSI Applications

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NER: Modeling and Design of Nanotube-Based On-Chip Interconnect Solutions for Future VLSI Applications (ECCS-0709334)Objective:In future nanoscale integrated circuits, process technology scaling coupled with increasing operating frequencies will exacerbate the resistivity, electromigration, and delay problems that already plague interconnect in today's designs. As CMOS technology is pushed to its basic physical limits, alternate technologies are required for on-chip communication. In this project, we will explore carbon nanotube-based interconnect solutions for future VLSI applications.Intellectual Merit: Metallic carbon nanotubes are a promising replacement for on-chip copper interconnect due to their large conductivity and current carrying capabilities. We will investigate and develop equivalent circuit models to facilitate the development of nanotube-based interconnect solutions. Using the proposed models, we will examine the performance and reliability of nanotube interconnect structures in future process technologies. Nanotube-based interconnect solutions have the potential to revolutionize next generation integrated circuits for a large array of VLSI applications. Broader Impacts:In addition, the educational and outreach programs associated with the proposed research, which target minority, undergraduate, and graduate students, will be instrumental in promoting the scientific principles related to carbon nanotubes and nanoscale integrated circuits.