U.S.-Egypt Cooperative Research: A Novel Flash Fast-Locking Wide-Band Digital Phase-Locked Loop

美埃合作研究：新型闪存快速锁定宽带数字锁相环

• 批准号: 0710887
• 负责人: Mahmoud Wagdy
• 金额: $ 3万
• 依托单位: California State University-Long Beach Foundation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-01 至 2010-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0710887&HistoricalAwards=false
• 关键词: U.S.; Egypt; Cooperative; Research; Novel

0710887WagdyDescription: This project supports collaborative research by Dr. Mahmoud Wagdy, Department of Electrical Engineering, California State University-Long Beach. The Egyptian collaborator is Dr. Hamed El-Simary at the Electronics Research Institute, Cairo, Egypt. They plan to investigate a novel flash fast locking wide-band Digital Phase-Locked Loop (DPLL). There are many applications (communications, industrial, etc.) which significantly influence information technology insofar as speed and throughput are concerned. These applications are Radio Frequency (RF) ones in the GHz frequency range, and thus require fast-locking digital phase-locked loops (DPLLs). The research will provide a working novel fast-locking DPLL in the GHz range ( 2 GHz) using 0.18 microm CMOS process, which is cheaper than other technologies such as SiGe, Bipolar, etc. The project objectives include: (1) a comparative study of various categories of fast-locking DPLLs employing: a mathematical algorithm to achieve fast convergence, nonlinear characteristics for the CP (charge pump) to change the convergence rate, feedback with the CP and PFD (phase frequency detector), or current-mode techniques; the existing literature includes tens of papers and patents, not thousands as in conventional DPLLs; the study will employ behavioral modeling tools such as Simulink, Verilog and/or VHDL, (2) designing (using Cadence/Mentor Graphics) the proposed novel fast-locking DPLL comprising two stages: a coarse-tuning stage based on a flash (parallel) algorithm, followed by fine-tuning stage similar to conventional DPLLs, (3) timing analysis to assess advantages over other techniques, derivation of closed-form formulae for lock time using actual hardware delays, as well as lock time analysis via behavioral modeling, (4) reduction of the following: lock time, frequency overshoot, phase noise (jitter), spurious signals, and static noise errors due to mismatches in PFD/CP, (5) investigating DPLL stability (via Simulink), parasitic awareness, RF issues (via Agilent ADS software), etc., and (6) fabrication, and hardware testing.Intellectual Merit: This research will fill a number of voids in the relatively recent field of digital fast-locking phase-locked loops. It will provide more complete understanding of the differences between various categories of these DPLLs via mathematical and behavioral modeling techniques. In particular, the research will provide a complete quantitative basis including closed-form formulae, for computation of the lock time, which is a critical performance parameter for many important applications. The proposal presents a novel wide-band DPLL using a flash algorithm, which is conceptually similar to the one employed by flash A/D converters; this algorithm is the counterpart of the slower successive-approximation algorithm employed by many fast-locking DPLLs.Broader Impacts: Because of the need for fast-locking DPLLs for cellular phones, spread-spectrum communications, information technology, and clock/data recovery (CDR) circuits, this research will benefit private industry, space agencies, and the society at large. The project will support graduate students for working on this international cooperative project. This project is being supported under the US-Egypt Joint Fund Program, which provides grants to scientists and engineers in both countries to carry out these cooperative activities.

0710887 Wagdy描述：该项目支持加州州立大学长滩海滩电气工程系Mahmoud Wagdy博士的合作研究。 埃及合作者是埃及开罗电子研究所的Hamed El-Simary博士。 他们计划研究一种新型的快速锁定宽带数字锁相环（DPLL）。有许多应用（通信，工业等）。这在速度和吞吐量方面显著地影响信息技术。这些应用是GHz频率范围内的射频（RF）应用，因此需要快速锁定数字锁相环（DPLL）。该研究将提供一种工作在GHz范围（2 GHz）的新型快速锁定DPLL，使用0.18微米CMOS工艺，这比其他技术（如SiGe，双极等）便宜。项目目标包括：（1）对采用以下技术的各种类型的快速锁定DPLL进行比较研究：一种数学算法，实现收敛速度快，针对CP的非线性特性（电荷泵）改变收敛速率，用CP和PFD反馈（相位频率检测器）或电流模式技术;现有文献包括数十篇论文和专利，而不是传统DPLL中的数千篇;该研究将采用行为建模工具，如Simulink，Verilog和/或VHDL，（2）设计（使用Cadence/Mentor Graphics）所提出的新型快速锁定DPLL包括两个级：基于闪光灯的粗调阶段（并行）算法，随后是类似于常规DPLL的微调阶段，（3）时序分析以评估优于其它技术的优点，使用实际硬件延迟推导锁定时间的闭合形式公式，以及通过行为建模进行锁定时间分析，（4）减少以下各项：锁定时间、频率过冲、相位噪声（抖动）、寄生信号和由于PFD/CP失配引起的静态噪声误差;（5）研究DPLL稳定性（通过Simulink）、寄生感知、RF问题（通过Agilent ADS软件）等，（6）制作和硬件测试。智力上的优点：这项研究将填补数字快速锁定锁相环这一相对较新的领域中的一些空白。它将通过数学和行为建模技术提供对这些DPLL的各种类别之间的差异的更完整的理解。特别是，研究将提供一个完整的定量基础，包括封闭形式的公式，计算的锁定时间，这是一个关键的性能参数，许多重要的应用。 该提案提出了一种使用闪存算法的新型宽带DPLL，该算法在概念上类似于闪存A/D转换器所采用的算法;该算法是许多快速锁定DPLL所采用的较慢逐次逼近算法的对应算法。由于蜂窝电话、扩频通信、信息技术和时钟/数据恢复（CDR）电路需要快速锁定DPLL，这项研究将使私营企业、航天机构和整个社会受益。该项目将支持研究生从事这一国际合作项目。 该项目得到了美国-埃及联合基金方案的支持，该方案向两国的科学家和工程师提供赠款，以开展这些合作活动。