CSR---EHS: A VLIW Architecture and Compiler Framework for Time Predictability

CSR---EHS：用于时间可预测性的 VLIW 架构和编译器框架

• 批准号: 0720502
• 负责人: Wei Zhang
• 金额: --
• 依托单位: Southern Illinois University at Carbondale
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-01 至 2010-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0720502&HistoricalAwards=false
• 关键词: CSR; EHS; VLIW; Architecture; Compiler

Time predictability is vital to the correctness of hard real-time and safety-critical systems, such as automotive and aircraft control systems. However, the architectural design of modern microprocessors has mainly concentrated on improving the average-case performance by using techniques such as cache memory, branch prediction, and speculative execution, which can significantly compromise the time predictability of computing and make the accurate worst-case execution time (WCET) analysis extremely difficult. This project is designing a highly time-predictable VLIW architecture while keeping the advantages of VLIW architectures in terms of high performance and hardware simplicity. The project also studies novel compiler techniques to support the time-predictable VLIW architecture, including scheduling-aware scratch-pad memory management, full and partial if-conversion with implicit path enumeration (IPE), compiler-directed nop insertion to remove pipeline timing effects, and WCET-oriented compiler optimizations. The success of this project is expected to accelerate the design, implementation, and deployment of time-predictable VLIW processors for a wide range of hard real-time applications, which can benefit both the embedded processor industry and the society. The developed software packages are made publicly available through the PI's research website.

时间可预测性对于艰苦的实时和关键安全系统（例如汽车和飞机控制系统）的正确性至关重要。但是，现代微处理器的建筑设计主要集中于通过使用诸如缓存内存，分支预测和投机执行等技术来改善平均案例性能，这可能会显着损害计算的时间可预测性，并使准确的最差案例执行时间（WCET）分析非常困难。 该项目正在设计一个高度时间预测的VLIW体系结构，同时在高性能和硬件简单性方面保持VLIW架构的优势。该项目还研究了新颖的编译器技术，以支持时间预测的VLIW体系结构，包括附表意识到的刮擦式内存管理，具有隐式路径枚举（IPE）的完整和部分IF转换，以编译器为导向的NOP插入以删除管道定时效应，以及与WCET方向的编译器优化。预计该项目的成功将加速可预测的VLIW处理器的设计，实施和部署，用于广泛的硬实时应用程序，这可以使嵌入式处理器行业和社会受益。开发的软件包可通过PI的研究网站公开获得。