CSR---EHS: A VLIW Architecture and Compiler Framework for Time Predictability

CSR---EHS：用于时间可预测性的 VLIW 架构和编译器框架

• 批准号: 0720502
• 负责人: Wei Zhang
• 金额: --
• 依托单位: Southern Illinois University at Carbondale
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-01 至 2010-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0720502&HistoricalAwards=false
• 关键词: CSR; EHS; VLIW; Architecture; Compiler

Time predictability is vital to the correctness of hard real-time and safety-critical systems, such as automotive and aircraft control systems. However, the architectural design of modern microprocessors has mainly concentrated on improving the average-case performance by using techniques such as cache memory, branch prediction, and speculative execution, which can significantly compromise the time predictability of computing and make the accurate worst-case execution time (WCET) analysis extremely difficult. This project is designing a highly time-predictable VLIW architecture while keeping the advantages of VLIW architectures in terms of high performance and hardware simplicity. The project also studies novel compiler techniques to support the time-predictable VLIW architecture, including scheduling-aware scratch-pad memory management, full and partial if-conversion with implicit path enumeration (IPE), compiler-directed nop insertion to remove pipeline timing effects, and WCET-oriented compiler optimizations. The success of this project is expected to accelerate the design, implementation, and deployment of time-predictable VLIW processors for a wide range of hard real-time applications, which can benefit both the embedded processor industry and the society. The developed software packages are made publicly available through the PI's research website.

时间可预测性对于硬实时和安全关键系统（如汽车和飞机控制系统）的正确性至关重要。然而，现代微处理器的体系结构设计主要集中在通过使用诸如高速缓冲存储器、分支预测和推测执行等技术来提高平均情况下的性能，这些技术可以显著地损害计算的时间可预测性，并且使得准确的最坏情况执行时间（WCET）分析变得极其困难。 本项目在保持VLIW体系结构在高性能和硬件简单性方面的优势的同时，设计了一种高度时间可预测的VLIW体系结构。该项目还研究了新的编译器技术，以支持时间可预测的VLIW体系结构，包括嵌入式感知暂存器内存管理，完全和部分if转换与隐式路径枚举（IPE），编译器指导的nop插入，以消除管道的时间效应，和面向WCET的编译器优化。该项目的成功有望加速面向广泛的硬实时应用的时间可预测VLIW处理器的设计、实现和部署，这将使嵌入式处理器行业和社会受益。通过PI的研究网站公开提供开发的软件包。