CSR---EHS: A VLIW Architecture and Compiler Framework for Time Predictability

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Time predictability is vital to the correctness of hard real-time and safety-critical systems, such as automotive and aircraft control systems. However, the architectural design of modern microprocessors has mainly concentrated on improving the average-case performance by using techniques such as cache memory, branch prediction, and speculative execution, which can significantly compromise the time predictability of computing and make the accurate worst-case execution time (WCET) analysis extremely difficult. This project is designing a highly time-predictable VLIW architecture while keeping the advantages of VLIW architectures in terms of high performance and hardware simplicity. The project also studies novel compiler techniques to support the time-predictable VLIW architecture, including scheduling-aware scratch-pad memory management, full and partial if-conversion with implicit path enumeration (IPE), compiler-directed nop insertion to remove pipeline timing effects, and WCET-oriented compiler optimizations. The success of this project is expected to accelerate the design, implementation, and deployment of time-predictable VLIW processors for a wide range of hard real-time applications, which can benefit both the embedded processor industry and the society. The developed software packages are made publicly available through the PI's research website.