CSR---SMA: A CAD framework to support the effective application of redundancy at the switch/architectural level for future technologies having high defect rates and variations

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Computer-aided-design systems for digital circuits interfaces with computing technologies and fabrication processes that exhibit high levels of variations, defect densities and noise susceptibility. A direct extrapolation and ad-hoc application of existing defect-tolerance (DT) and fault-tolerance (FT) techniques erodes much of the benefits of new technologies. The objective of this research is to develop a systematic framework for design and test of digital systems that optimizes a specified combination of cost, performance and power for nanometer technologies.A framework for efficient application of existing and new DT and FT techniques, including the use of spares, task rescheduling, coding and DFM rules is being developed. This framework works in conjunction with existing design flows and includes components spanning the levels of technology (variations/defects), layout, circuit, logic, architecture and system. Key innovations are embodied in new techniques for identifying efficient ways of assigning spares, reconfiguring around faulty modules, and modifying selected parts of a module to improve yield. To obtain optimality, a design explorer is being developed to efficiently search the space of alternative designs. This research will provide the first framework for design of digital systems for the remaining years of CMOS scaling and beyond. We will train graduate and undergraduate students in this methodology of the future and share our results with academic and industrial colleagues. This research will provide immense benefits to society by being a key enabler of an era of inexpensive and powerful digital devices with significant educational, health and security functions.