SGER: Hardward/Software Partitioning for Multiprocessor and Multicore Acceleration
SGER:用于多处理器和多核加速的硬件/软件分区
基本信息
- 批准号:0745490
- 负责人:
- 金额:$ 3.69万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2007
- 资助国家:美国
- 起止时间:2007-09-01 至 2008-08-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Field programmable gate arrays (FPGAs) are capable of speedups ranging from the 10s to 1,000s over traditional general-purpose processors (CPUs) on frequently executed code segments. However, such speedups occur only when the capability of the FPGA is fully utilized. It is becoming increasingly apparent that the bandwidth into and out of the FPGA can quickly become a limiting factor in its utilization. It is possible to design and map a large circuit on an FPGA but not have the bandwidth to keep it busy. The proposed project explores techniques for partitioning code implemented either in hardware on FPGAs or as software running on CPUs of a multicore multiprocessor system that enable efficient use of parallel computing resources. Three specific models of CPU/FPGA acceleration are explored that span a wide range of computing platforms: from embedded systems at the low end to high-performance multiprocessor systems at the high end. These models, along with applications suitable for the intended platforms, are used to identify and quantify performance parameters of CPU/FPGA interaction that drive the proposed partitioning techniques. This exploratory research may pave they way for the design, implementation and evaluation of automated hardware/software partitioning techniques for CPU/FPGA multicore multiprocessor systems envisioned to be pervasive across the computing spectrum in the near future.
现场可编程门阵列(FPGA)能够在频繁执行的代码段上比传统的通用处理器(CPU)加速10秒到1,000秒。然而,这种加速只有在FPGA的能力得到充分利用时才会发生。越来越明显的是,进出FPGA的带宽可能很快成为其利用率的限制因素。可以在FPGA上设计和映射大型电路,但没有足够的带宽使其保持忙碌。 拟议的项目探讨的技术分区代码实现在FPGA硬件或软件上运行的多核多处理器系统的CPU,使并行计算资源的有效利用。三个特定的CPU/FPGA加速模型,探讨了跨越广泛的计算平台:从低端的嵌入式系统到高端的高性能多处理器系统。这些模型,沿着与适用于预期平台的应用程序,用于识别和量化驱动所提出的分区技术的CPU/FPGA交互的性能参数。这种探索性的研究可能铺平了道路的设计,实现和评估的自动化硬件/软件划分技术的CPU/FPGA多核多处理器系统设想在不久的将来是普遍的计算频谱。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Walid Najjar其他文献
High performance FPGA and GPU complex pattern matching over spatio-temporal streams
- DOI:
10.1007/s10707-014-0217-3 - 发表时间:
2014-08-26 - 期刊:
- 影响因子:2.600
- 作者:
Roger Moussalli;Ildar Absalyamov;Marcos R. Vieira;Walid Najjar;Vassilis J. Tsotras - 通讯作者:
Vassilis J. Tsotras
On the Hu 2003 Plasticity Criterion
- DOI:
10.1007/s11665-023-08700-z - 发表时间:
2023-09-12 - 期刊:
- 影响因子:2.000
- 作者:
Walid Najjar;Imed Ghaouss;Idriss Tiba;Philippe Dal Santo - 通讯作者:
Philippe Dal Santo
Walid Najjar的其他文献
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{{ truncateString('Walid Najjar', 18)}}的其他基金
SHF:Small: Automatic Generation of Hardware Threads on Programmable Fabrics
SHF:Small:在可编程结构上自动生成硬件线程
- 批准号:
1219180 - 财政年份:2012
- 资助金额:
$ 3.69万 - 项目类别:
Standard Grant
CPA-CSA: Hardware Support for FPGA-Based Code Acceleration
CPA-CSA:基于 FPGA 代码加速的硬件支持
- 批准号:
0811416 - 财政年份:2008
- 资助金额:
$ 3.69万 - 项目类别:
Continuing Grant
Reliability, Performability and Scalability of Large-Scale Distributed Systems
大规模分布式系统的可靠性、性能和可扩展性
- 批准号:
9010240 - 财政年份:1990
- 资助金额:
$ 3.69万 - 项目类别:
Standard Grant