CPA-CSA: Hardware Support for FPGA-Based Code Acceleration

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Field Programmable Gate Arrays (FPGAs) are hardware devices on which a circuit can be mapped under software control. The recent growth in both size and speed of FPGAs have made them attractive platforms for hardware-based code acceleration. In this novel paradigm, frequently executed code fragments are expressed as a circuit that is mapped onto one or more FPGAs. This paradigm benefits from a very large degree of parallelism as well as increased efficiency of execution. It has been shown to result in speedups ranging from the 10s to the 1,000s over traditional processors for frequently executed code segments in applications such as bioinformatics, molecular dynamics, image and video processing, and intrusion detection systems. The main obstacle to a wider acceptance of this paradigm is its programmability. Although several projects have proposed tools that translate high-level languages (HLLs) to hardware, none has proven to be suitable for hardware acceleration.The objective of this proposal is to develop hardware support for FPGA-based code acceleration with specific emphasis on component-based data path construction and efficient memory interfaces and allocation. This component-based programming of FPGAs supports code reuse and modularity and as such can greatly facilitate the development of application codes for FPGA-based accelerators, thereby providing a great boost to a wide array of high-performance computing challenges.