CPA-CSA: Hardware Support for FPGA-Based Code Acceleration

CPA-CSA：基于 FPGA 代码加速的硬件支持

• 批准号: 0811416
• 负责人: Walid Najjar
• 金额: $ 23万
• 依托单位: University of California-Riverside
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-15 至 2012-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811416&HistoricalAwards=false
• 关键词: CPA; CSA; Hardware; Support; FPGA

Field Programmable Gate Arrays (FPGAs) are hardware devices on which a circuit can be mapped under software control. The recent growth in both size and speed of FPGAs have made them attractive platforms for hardware-based code acceleration. In this novel paradigm, frequently executed code fragments are expressed as a circuit that is mapped onto one or more FPGAs. This paradigm benefits from a very large degree of parallelism as well as increased efficiency of execution. It has been shown to result in speedups ranging from the 10s to the 1,000s over traditional processors for frequently executed code segments in applications such as bioinformatics, molecular dynamics, image and video processing, and intrusion detection systems. The main obstacle to a wider acceptance of this paradigm is its programmability. Although several projects have proposed tools that translate high-level languages (HLLs) to hardware, none has proven to be suitable for hardware acceleration.The objective of this proposal is to develop hardware support for FPGA-based code acceleration with specific emphasis on component-based data path construction and efficient memory interfaces and allocation. This component-based programming of FPGAs supports code reuse and modularity and as such can greatly facilitate the development of application codes for FPGA-based accelerators, thereby providing a great boost to a wide array of high-performance computing challenges.

现场可编程门阵列(现场可编程门阵列)是一种硬件设备，可以在软件控制下在其上映射电路。最近在大小和速度上的增长使其成为基于硬件的代码加速的有吸引力的平台。在该新范例中，频繁执行的代码片段被表示为映射到一个或多个FPGA上的电路。这种范例得益于很大程度的并行性以及更高的执行效率。已经证明，对于生物信息学、分子动力学、图像和视频处理以及入侵检测系统等应用程序中频繁执行的代码段，它比传统处理器的加速比从10%到1000%不等。广泛接受这一范例的主要障碍是它的可编程性。虽然已经有几个项目提出了将高级语言(HLL)转换为硬件的工具，但没有一个项目被证明适合于硬件加速。该建议的目标是开发基于FPGA的代码加速的硬件支持，重点是基于组件的数据路径构建和高效的内存接口和分配。这种基于组件的FPGA编程支持代码重用和模块化，因此可以极大地促进基于FPGA的加速器应用代码的开发，从而极大地推动了一系列高性能计算挑战。