CPA-CSA: Hardware Support for FPGA-Based Code Acceleration

现场可编程门阵列（FPGA）是硬件设备，电路可以在软件控制下映射到其上。最近FPGA在尺寸和速度上的增长使其成为基于硬件的代码加速的有吸引力的平台。在这种新颖的范例中，频繁执行的代码片段被表示为映射到一个或多个FPGA上的电路。 这种范例受益于非常大程度的并行性以及更高的执行效率。它已经被证明可以在生物信息学、分子动力学、图像和视频处理以及入侵检测系统等应用中频繁执行的代码段上比传统处理器加速10秒到1,000秒。更广泛地接受这种范式的主要障碍是它的可编程性。虽然有几个项目已经提出了工具，翻译高级语言（HLL）的硬件，没有被证明是适合的硬件acceleration.The本提案的目标是开发硬件支持基于FPGA的代码加速，特别强调基于组件的数据路径建设和高效的内存接口和分配。FPGA的这种基于组件的编程支持代码重用和模块化，因此可以极大地促进基于FPGA的加速器的应用程序代码的开发，从而为各种高性能计算挑战提供极大的推动。

Field Programmable Gate Arrays (FPGAs) are hardware devices on which a circuit can be mapped under software control. The recent growth in both size and speed of FPGAs have made them attractive platforms for hardware-based code acceleration. In this novel paradigm, frequently executed code fragments are expressed as a circuit that is mapped onto one or more FPGAs. This paradigm benefits from a very large degree of parallelism as well as increased efficiency of execution. It has been shown to result in speedups ranging from the 10s to the 1,000s over traditional processors for frequently executed code segments in applications such as bioinformatics, molecular dynamics, image and video processing, and intrusion detection systems. The main obstacle to a wider acceptance of this paradigm is its programmability. Although several projects have proposed tools that translate high-level languages (HLLs) to hardware, none has proven to be suitable for hardware acceleration.The objective of this proposal is to develop hardware support for FPGA-based code acceleration with specific emphasis on component-based data path construction and efficient memory interfaces and allocation. This component-based programming of FPGAs supports code reuse and modularity and as such can greatly facilitate the development of application codes for FPGA-based accelerators, thereby providing a great boost to a wide array of high-performance computing challenges.