CAREER: Communication-Centric Chip Multiprocessor Design

随着CMOS工艺中特征尺寸的不断缩小，已经能够在单个芯片中集成大量的器件，如内核、高速缓存和其他特殊引擎。芯片多处理器(CMPS)的日益普及带来了以通信为中心的系统的到来，其中互连体系结构的设计对整个系统的性能以及芯片的功耗和面积有着重要的影响。为了克服传统的互连问题，片上网络(NoC)利用基于交换机的网络，已经被广泛地接受为一种很有前途的芯片范围内通信的架构。虽然片上系统设计已经有了大量的研究，但目前还缺乏一个统一的设计方法学来整合系统和片上系统设计，研究人员正在开发一种全面的设计范式来探索片上互连设计空间，特别是它如何与CMP体系结构的其余部分交互。这项研究计划由四个相互交织的研究目标组成。首先，开发了模拟试验台和流量分析方法，以了解应用程序和系统体系结构之间的相互影响。流量分析工具用于捕获CMPS中各种应用的运行时行为。其次，提供了在当前和未来技术世代的电力和区域预算内实现高性能和可预测性能的解决方案。第三，PI正在为CMP存储系统开发特定于域的NoC设计。作为最后一个目标，国际和平研究所探讨了下一代化学机械加工技术未来应用所带来的新机遇和新挑战。通过现有的和新的研究生课程，以及本科生的研究计划，研究被整合到教育课程中。

The ever-shrinking feature size in CMOS process technology has enabled the integration of a large number of devices such as cores, caches, and other special engines in a single chip. The growing popularity of Chip Multiprocessors (CMPs) has ushered in the arrival of a communication-centric system where the design of interconnection architecture has a significant impact on the overall system performance as well as power dissipation and area of a chip. To overcome traditional interconnects problems, Network-on-chip (NoC), using switch-based networks, has been widely accepted as a promising architecture to orchestrate chip-wide communication. Although there has been significant research on NoC designs, there is still a lack of a unified design methodology integrating system and NoC design.The investigator is developing a comprehensive design paradigm for exploring the on-chip interconnect design space, especially focusing on how it interacts with the rest of the CMP architecture. This research program is comprised of four intertwined research objectives. First, simulation testbeds and traffic analysis methodologies are developed to understand the interplay between applications and system architecture. Traffic analysis tools are used to capture the runtime behavior of various applications in CMPs. Second, solutions for high and predictable performance within power and area budgets in current and future technology generations are provided. Third, the PI is developing a domain specific NoC design for CMP memory systems. As the last objective, the PI explores new opportunities and challenges posed by future applications of next-generation CMP. The research is integrated into the education curriculum, through existing and new graduate courses, and in undergraduate research programs.