CAREER: Communication-Centric Chip Multiprocessor Design

职业：以通信为中心的芯片多处理器设计

• 批准号: 0845998
• 负责人: Eun Jung Kim
• 金额: $ 40万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-03-01 至 2014-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0845998&HistoricalAwards=false
• 关键词: CAREER; Communication; Centric; Chip; Multiprocessor

The ever-shrinking feature size in CMOS process technology has enabled the integration of a large number of devices such as cores, caches, and other special engines in a single chip. The growing popularity of Chip Multiprocessors (CMPs) has ushered in the arrival of a communication-centric system where the design of interconnection architecture has a significant impact on the overall system performance as well as power dissipation and area of a chip. To overcome traditional interconnects problems, Network-on-chip (NoC), using switch-based networks, has been widely accepted as a promising architecture to orchestrate chip-wide communication. Although there has been significant research on NoC designs, there is still a lack of a unified design methodology integrating system and NoC design.The investigator is developing a comprehensive design paradigm for exploring the on-chip interconnect design space, especially focusing on how it interacts with the rest of the CMP architecture. This research program is comprised of four intertwined research objectives. First, simulation testbeds and traffic analysis methodologies are developed to understand the interplay between applications and system architecture. Traffic analysis tools are used to capture the runtime behavior of various applications in CMPs. Second, solutions for high and predictable performance within power and area budgets in current and future technology generations are provided. Third, the PI is developing a domain specific NoC design for CMP memory systems. As the last objective, the PI explores new opportunities and challenges posed by future applications of next-generation CMP. The research is integrated into the education curriculum, through existing and new graduate courses, and in undergraduate research programs.

CMOS工艺技术中不断缩小的特征尺寸使得能够在单个芯片中集成大量器件，例如内核、高速缓存和其他特殊引擎。芯片多处理器（CMP）的日益普及已经迎来了以通信为中心的系统的到来，其中互连结构的设计对整个系统的性能以及芯片的功耗和面积具有显著的影响。为了克服传统的互连问题，片上网络（NoC），使用基于交换机的网络，已被广泛接受为一个有前途的架构，以协调芯片范围内的通信。虽然NoC设计已经有了大量的研究，但仍然缺乏一个统一的设计方法来集成系统和NoC设计，研究人员正在开发一个全面的设计范式来探索片上互连设计空间，特别是关注它如何与CMP架构的其他部分相互作用。该研究计划由四个相互交织的研究目标组成。首先，开发模拟测试平台和流量分析方法，以了解应用程序和系统架构之间的相互作用。 流量分析工具用于捕获CMP中各种应用程序的运行时行为。其次，在当前和未来的技术世代中，提供在功率和面积预算内实现高和可预测性能的解决方案。第三，PI正在为CMP存储系统开发特定领域的NoC设计。作为最后一个目标，PI探索了下一代CMP未来应用所带来的新机遇和挑战。该研究被纳入教育课程，通过现有的和新的研究生课程，并在本科研究计划。