SHF: Small: Communication Architecture Designs for Future Heterogeneous Systems

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Big data have emerged in various data-centric applications including deep learning and graph processing. These applications show characteristics such as stream processing or irregular data access patterns. However, modern CPU-based architectures with general-purpose instruction-set architectures and memory incur large performance overheads. To remedy this problem, adopting application-specific components and heterogeneous processing units, like GPUs and accelerators, is gaining popularity. As data size increases, more efficient data processing is required, which demands high-density computation and larger bandwidth for data movements, which motivates the need for large-scale heterogeneous systems. Unlike CPU-based systems, the communication in heterogeneous systems may have dynamic and flexible requirements for both latency and throughput depending on applications and involved processors. In addition, since designing a large monolithic chip is impractical due to high cost and low yield rate, cost-effective and design-efficient chiplet-based modular designs are preferred. This project studies the design of communication architectures for heterogeneous systems to accelerate data-centric applications. It includes research in the fundamentals of interconnects such as deadlock-freedom, routing, flow control, and topology designs, to provide correct functionalities and fulfill heterogeneous communication requirements. To reduce data movements inside the architectures, in-network computing and communication-acceleration solutions through specialization will be investigated to improve performance and energy efficiency of the heterogeneous systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.