SHF: Small: High Performance On-Chip Interconnects Design for Multicore Accelerators

SHF：小型：适用于多核加速器的高性能片上互连设计

• 批准号: 1423433
• 负责人: Eun Jung Kim
• 金额: $ 45万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-07-15 至 2018-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1423433&HistoricalAwards=false
• 关键词: SHF; Small; Performance; Chip; Interconnects

Advances in technology have made it possible to accommodate an increasing number of transistors on a die, enabling Multicore Accelerators like Graphics Processing Units(GPUs) by integrating diverse components on a single chip. GPUs have recently gained attention as a cost-effective approach for data parallel architectures, and the fast scaling of the GPUs increases the importance of designing an ideal on-chip interconnection network, which significantly impacts the overall system performance.In this project, we propose to develop a framework for high-performance andenergy-efficient on-chip network mechanisms in synergy with Multicore Accelerator architectures. The desirable properties of a target on-chip network include re-usabilityacross a wide range of Multicore Accelerator architectures, maximization of the use ofrouting resources, and support for reliable and energy-efficient data transfer.This project will make significant advances in understanding the interplay between Multicore Accelerator and Network-on-Chip (NoC) architectures, which leads us toscalable solutions for performance, area and energy.While the major communication of Chip Multiprocessor (CMP) systems is core-to-corefor shared caches, major traffic of Multicore Accelerators is core-to-memory, which makes the memory controllers hot spots. Since Multicore Accelerators execute manythreads in order to hide memory latency, it is critical for the underlying NoC to provide high bandwidth.The key contributions expected from the project are: (1) building a simulation testbed and analyzing the behavior of on-chip traffic workloads in MulticoreAccelerators; (2) proposing mechanisms for a high-performance and energy-efficient NoC by utilizing emerging memory and NoC technologies in addition to novel topologiesand routing mechanisms; (3) developing methodologies at the NoC level that will support data prefetching mechanisms in the Multicore Accelerators; and (4) providingmulticast support and packet coalescing in the on-chip network to guarantee bettersystem throughput. The results from this project are likely to foster new research directions in severalareas of Computer Architecture and Parallel Computing. Also, high-performance and energy-aware computing and communication research is applicable to other areas,such as Embedded Systems and Cloud Computing. We will develop web-based tutorials to present and disseminate the results of this project, including tools and techniques, to a broad audience.

技术的进步使得在一个芯片上容纳越来越多的晶体管成为可能，通过在单个芯片上集成各种组件，实现了图形处理单元（GPU）等多核加速器。GPU作为一种高性价比的数据并行架构，近年来受到了广泛关注，而GPU的快速扩展使得设计一个理想的片上互连网络变得越来越重要，这对整个系统的性能有着重要的影响。目标片上网络的理想属性包括跨各种多核加速器架构的可重用性，路由资源的最大化使用，以及对可靠和节能的数据传输的支持。该项目将在理解多核加速器和片上网络（NoC）架构之间的相互作用方面取得重大进展，这将引导我们找到可扩展的性能解决方案，虽然芯片多处理器（CMP）系统的主要通信是用于共享高速缓存的核到核，但是多核加速器的主要业务是核到存储器，这使得存储器控制器成为热点。由于多核加速器需要执行多个线程来隐藏内存延迟，因此底层片上网络必须提供高带宽，本项目的主要贡献包括：（1）建立一个仿真测试平台，分析多核加速器中片上流量负载的行为;（2）提出了一种高性能、高能效的片上网络机制，该机制利用了新兴的存储器和片上网络技术以及新的拓扑结构和路由机制;（3）在片上网络层面开发支持多核加速器中数据预取机制的方法;（4）在片上网络中提供多播支持和数据包合并，以保证更好的系统吞吐量。该项目的结果可能会在计算机体系结构和并行计算的几个领域中促进新的研究方向。此外，高性能和节能计算和通信研究也适用于其他领域，如嵌入式系统和云计算。我们将开发基于网络的教程，向广大受众展示和传播该项目的成果，包括工具和技术。