SHF: Small: High Performance On-Chip Interconnects Design for Multicore Accelerators

技术的进步使在芯片上容纳越来越多的晶体管成为可能，通过将不同的组件集成到单个芯片上，实现了图形处理单元(GPU)等多核加速器。GPU作为一种高性价比的数据并行架构方法近年来受到了广泛的关注，而GPU的快速扩展增加了设计理想的片上互连网络的重要性，而片上互连网络的设计将显著影响系统的整体性能。目标片上网络的理想特性包括在广泛的多核加速器体系结构上的可重用性，最大限度地利用空闲资源，以及支持可靠和节能的数据传输。该项目将在理解多核加速器和片上网络(NoC)体系结构之间的相互作用方面取得重大进展，这将导致我们在性能、面积和能量方面找到可扩展的解决方案。虽然芯片多处理器(CMP)系统的主要通信是用于共享缓存的核到核，但多核加速器的主要流量是核到内存，这使得内存控制器成为热点。由于多核加速器执行大量线程以隐藏存储延迟，因此提供高带宽对底层片上网络至关重要。该项目的主要贡献是：(1)建立模拟试验台，分析多核加速器中片上流量负载的行为；(2)提出利用新兴的内存和片上网络技术以及新的拓扑和路由机制来实现高性能和高能效的片上网络；(3)在片上网络级别开发支持多核加速器中的数据预取机制的方法；以及(4)在片上网络中提供组播支持和分组合并，以保证更好的系统吞吐量。这个项目的结果可能会在计算机体系结构和并行计算的几个领域培养新的研究方向。此外，高性能和节能的计算和通信研究也适用于其他领域，如嵌入式系统和云计算。我们将开发基于网络的教程，向广大受众展示和传播该项目的成果，包括工具和技术。

Advances in technology have made it possible to accommodate an increasing number of transistors on a die, enabling Multicore Accelerators like Graphics Processing Units(GPUs) by integrating diverse components on a single chip. GPUs have recently gained attention as a cost-effective approach for data parallel architectures, and the fast scaling of the GPUs increases the importance of designing an ideal on-chip interconnection network, which significantly impacts the overall system performance.In this project, we propose to develop a framework for high-performance andenergy-efficient on-chip network mechanisms in synergy with Multicore Accelerator architectures. The desirable properties of a target on-chip network include re-usabilityacross a wide range of Multicore Accelerator architectures, maximization of the use ofrouting resources, and support for reliable and energy-efficient data transfer.This project will make significant advances in understanding the interplay between Multicore Accelerator and Network-on-Chip (NoC) architectures, which leads us toscalable solutions for performance, area and energy.While the major communication of Chip Multiprocessor (CMP) systems is core-to-corefor shared caches, major traffic of Multicore Accelerators is core-to-memory, which makes the memory controllers hot spots. Since Multicore Accelerators execute manythreads in order to hide memory latency, it is critical for the underlying NoC to provide high bandwidth.The key contributions expected from the project are: (1) building a simulation testbed and analyzing the behavior of on-chip traffic workloads in MulticoreAccelerators; (2) proposing mechanisms for a high-performance and energy-efficient NoC by utilizing emerging memory and NoC technologies in addition to novel topologiesand routing mechanisms; (3) developing methodologies at the NoC level that will support data prefetching mechanisms in the Multicore Accelerators; and (4) providingmulticast support and packet coalescing in the on-chip network to guarantee bettersystem throughput. The results from this project are likely to foster new research directions in severalareas of Computer Architecture and Parallel Computing. Also, high-performance and energy-aware computing and communication research is applicable to other areas,such as Embedded Systems and Cloud Computing. We will develop web-based tutorials to present and disseminate the results of this project, including tools and techniques, to a broad audience.