Reprogrammable Nanowire Electronics - ReproNano III

可重编程纳米线电子器件 - ReproNano III

• 批准号: 191017672
• 负责人: Professor Dr.-Ing. Walter Michael Weber
• 金额: --
• 依托单位: Institut für Festkörperelektronik
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2011
• 资助国家: 德国
• 起止时间: 2010-12-31 至 2016-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/191017672?language=en
• 关键词: Reprogrammable; Nanowire; Electronics; ReproNano; III

Repronano aims to study novel nanowire based transistors and circuits exploiting their inherent controllable multifunctionality at the device level to yield fine grain reprogrammable electronics. Different to coarse grain reprogrammable circuits like Field Programmable Gate Arrays (FPGAs), where signals are routed to predefined and static logic blocks, fine grain reconfigurable electronics provide a functional modification of the smallest functional units. The concept aims at new opportunities in circuit and system design reducing transistor count and sparing routing delays as compared to classical CMOS based circuits. The basic element is the reconfigurable nanowire transistor (RFET). Its potential has been recently verified in building XOR rich circuits, multi-input logic and hardware security systems. By virtue of a plurality of gate electrodes acting on the junctions the RFET delivers p- and n- FET characteristics as selected by a program signal. Accordingly, a single MOS device technology results and no doping is necessary to build low-operation-power complementary circuits.In Repronano, reconfigurable nanowire transistors shall be built on a silicon on insulator (SOI) basis. The basics steps towards establishing circuit maturity were set in the preceding Repronano funding phase: symmetry of IV characteristics, scaling and performance analysis as well as basic concepts of logical combinatorial circuits. The symmetry adjustment scheme by elastic strain incorporation developed at Repronano allows for scalability of the device. Indeed, up to the submission of this proposal it is the only symmetry method from many groups working on this topic that delivers a circuit maturity.Within the requested project, SOI RFET devices and circuits will be built. In addition to dually gated RFETs, devices with multiple independent gates (MIG) will be demonstrated, further increasing the expressive diversity per device, without affecting on-currents. To lower operation voltages and to enhance device miniaturization surround - high-k / metal gate stacks will be used. To increase on-currents and to decrease the access resistance and capacitances, multiple parallel nanowires will be integrated. This will also allow for accurate capacitance-voltage (CV) characterization with a high precision capacitance loss bridge. 3D finite element device and process simulations will support device verification and predictive design. From electrical measurements and simulation results table models for circuit simulations will be set-up. Unit cells will be designed and novel combinational gates as well as sequential logic circuits will be developed. The impact of fine grain reconfigurability shall be studied and compared to CMOS in terms of delay, area and power consumption. A selection of circuits will be fabricated and demonstrated e.g. a reconfigurable single bit adder. The influence of process variability on the electrical metrics and circuit operation will be studied.

Repronano的目标是研究基于纳米线的新型晶体管和电路，在器件级利用其固有的可控多功能性来生产细颗粒可重新编程的电子产品。与粗粒度可编程电路（如现场可编程门阵列（fpga））不同，信号被路由到预定义的静态逻辑块，细粒度可重构电子设备提供最小功能单元的功能修改。与传统的CMOS电路相比，该概念旨在减少晶体管数量和节省路由延迟的电路和系统设计的新机会。基本元件是可重构纳米线晶体管（RFET）。它的潜力最近在构建异或富电路、多输入逻辑和硬件安全系统中得到了验证。通过作用于结上的多个栅极电极，该FET提供由程序信号选择的p-和n- FET特性。因此，采用单一MOS器件技术，无需掺杂即可构建低运行功率互补电路。在Repronano中，可重构的纳米线晶体管将建立在绝缘体上硅（SOI）的基础上。建立电路成熟度的基本步骤是在之前的Repronano资助阶段设定的：IV特征的对称性，缩放和性能分析以及逻辑组合电路的基本概念。在Repronano开发的弹性应变结合的对称调整方案允许设备的可扩展性。事实上，在提交此提案之前，它是许多研究该主题的小组中唯一提供电路成熟度的对称方法。在要求的项目中，将建造SOI RFET器件和电路。除了双门控rfet外，还将展示具有多个独立门（MIG）的器件，进一步增加每个器件的表达多样性，而不影响导通电流。为了降低工作电压和增强器件小型化，将使用高k /金属栅极堆叠。为了增加导通电流，降低接入电阻和电容，将集成多个并联纳米线。这也将允许精确的电容电压（CV）表征与高精度电容损耗桥。三维有限元设备和工艺模拟将支持设备验证和预测设计。从电测量和仿真结果表模型电路仿真将建立。单元单元将被设计，新的组合门和顺序逻辑电路将被开发。研究细粒可重构性的影响，并与CMOS在延迟、面积和功耗方面进行比较。将制作并演示一系列电路，例如可重构的单位加法器。过程可变性对电气指标和电路运行的影响将被研究。

项目成果

Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

• DOI: 10.1109/tvlsi.2018.2884646
• 发表时间: 2019-03-01
• 期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
• 影响因子: 2.8
• 作者: Rai, Shubham;Trommer, Jens;Kumar, Akash
• 通讯作者: Kumar, Akash

Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors

• DOI: 10.1109/led.2013.2290555
• 发表时间: 2014-01-01
• 期刊: IEEE ELECTRON DEVICE LETTERS
• 影响因子: 4.9
• 作者: Trommer, Jens;Heinzig, Andre;Weber, Walter Michael
• 通讯作者: Weber, Walter Michael

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

• DOI: 10.1088/1361-6633/aa56f0
• 发表时间: 2017-04
• 期刊: Reports on Progress in Physics
• 影响因子: 18.1
• 作者: W. Weber;T. Mikolajick

Stress-Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors

可重构硅纳米线晶体管的应力相关性能优化

• DOI: 10.1109/led.2015.2471103
• 发表时间: 2015
• 期刊: IEEE Electron Device Letters
• 影响因子: 4.9
• 作者: T. Baldauf;A. Heinzig;J. Trommer;T. Mikolajick;W. M. Weber
• 通讯作者: W. M. Weber

Operation regimes and electrical transport of steep slope Schottky Si-FinFETS

陡坡肖特基 Si-FinFET 的工作状态和电传输

• DOI: 10.1063/1.4975475
• 发表时间: 2017
• 期刊: Journal of Applied Physics
• 影响因子: 3.2
• 作者: D.-Y. Jeon;J. Zhang;J. Trommer;S.-J. Park;P.-E. Gaillardon;G. De Micheli;T. Mikolajick;W. M. Weber
• 通讯作者: W. M. Weber