Reprogrammable Nanowire Electronics - ReproNano III

Repronano的目标是研究新型纳米线晶体管和电路，利用其内在的可控多功能性，在器件水平上产生细粒度可重编程电子产品。与粗粒度可重编程电路（如现场可编程门阵列（FPGA））不同，其中信号被路由到预定义的静态逻辑块，细粒度可重配置电子器件提供最小功能单元的功能修改。该概念旨在为电路和系统设计提供新的机会，与经典的基于CMOS的电路相比，减少了晶体管数量并节省了布线延迟。基本元件是可重构纳米线晶体管（RFET）。它的潜力最近已被证明在建设异或丰富的电路，多输入逻辑和硬件安全系统。借助于作用在结上的多个栅电极，RFET传递由编程信号选择的p-和n-FET特性。因此，一个单一的MOS器件技术的结果，没有掺杂是必要的，以建立低操作功率互补circuits.In Repronano，可重构纳米线晶体管应建立在绝缘体上硅（SOI）的基础上。建立电路成熟度的基本步骤在之前的Repronano资助阶段已经确定：IV特性的对称性，缩放和性能分析以及逻辑组合电路的基本概念。在Repronano开发的通过弹性应变结合的对称性调整方案允许设备的可扩展性。事实上，在提交本提案之前，这是研究该主题的许多小组中唯一能够提供电路成熟度的对称方法。在所请求的项目中，将构建SOI RFET器件和电路。除了双门控RFFET之外，还将展示具有多个独立门（RFFET）的器件，进一步增加每个器件的表达多样性，而不影响导通电流。为了降低操作电压并增强器件小型化，将使用环绕高k/金属栅极堆叠。为了增加导通电流并减小接入电阻和电容，将集成多个平行的纳米线。这还将允许使用高精度电容损耗电桥进行准确的电容-电压（CV）表征。3D有限元器件和工艺模拟将支持器件验证和预测设计。根据电气测量和仿真结果表，将建立用于电路仿真的模型。将设计单元，并开发新型组合门和时序逻辑电路。应研究细粒度可重构性的影响，并在延迟、面积和功耗方面与CMOS进行比较。一个选择的电路将被制造和演示，例如一个可重构的单比特加法器。将研究工艺可变性对电气指标和电路操作的影响。

Repronano aims to study novel nanowire based transistors and circuits exploiting their inherent controllable multifunctionality at the device level to yield fine grain reprogrammable electronics. Different to coarse grain reprogrammable circuits like Field Programmable Gate Arrays (FPGAs), where signals are routed to predefined and static logic blocks, fine grain reconfigurable electronics provide a functional modification of the smallest functional units. The concept aims at new opportunities in circuit and system design reducing transistor count and sparing routing delays as compared to classical CMOS based circuits. The basic element is the reconfigurable nanowire transistor (RFET). Its potential has been recently verified in building XOR rich circuits, multi-input logic and hardware security systems. By virtue of a plurality of gate electrodes acting on the junctions the RFET delivers p- and n- FET characteristics as selected by a program signal. Accordingly, a single MOS device technology results and no doping is necessary to build low-operation-power complementary circuits.In Repronano, reconfigurable nanowire transistors shall be built on a silicon on insulator (SOI) basis. The basics steps towards establishing circuit maturity were set in the preceding Repronano funding phase: symmetry of IV characteristics, scaling and performance analysis as well as basic concepts of logical combinatorial circuits. The symmetry adjustment scheme by elastic strain incorporation developed at Repronano allows for scalability of the device. Indeed, up to the submission of this proposal it is the only symmetry method from many groups working on this topic that delivers a circuit maturity.Within the requested project, SOI RFET devices and circuits will be built. In addition to dually gated RFETs, devices with multiple independent gates (MIG) will be demonstrated, further increasing the expressive diversity per device, without affecting on-currents. To lower operation voltages and to enhance device miniaturization surround - high-k / metal gate stacks will be used. To increase on-currents and to decrease the access resistance and capacitances, multiple parallel nanowires will be integrated. This will also allow for accurate capacitance-voltage (CV) characterization with a high precision capacitance loss bridge. 3D finite element device and process simulations will support device verification and predictive design. From electrical measurements and simulation results table models for circuit simulations will be set-up. Unit cells will be designed and novel combinational gates as well as sequential logic circuits will be developed. The impact of fine grain reconfigurability shall be studied and compared to CMOS in terms of delay, area and power consumption. A selection of circuits will be fabricated and demonstrated e.g. a reconfigurable single bit adder. The influence of process variability on the electrical metrics and circuit operation will be studied.