Reprogrammable Nanowire Electronics - ReproNano III

点击翻译按钮获取中文摘要

Repronano aims to study novel nanowire based transistors and circuits exploiting their inherent controllable multifunctionality at the device level to yield fine grain reprogrammable electronics. Different to coarse grain reprogrammable circuits like Field Programmable Gate Arrays (FPGAs), where signals are routed to predefined and static logic blocks, fine grain reconfigurable electronics provide a functional modification of the smallest functional units. The concept aims at new opportunities in circuit and system design reducing transistor count and sparing routing delays as compared to classical CMOS based circuits. The basic element is the reconfigurable nanowire transistor (RFET). Its potential has been recently verified in building XOR rich circuits, multi-input logic and hardware security systems. By virtue of a plurality of gate electrodes acting on the junctions the RFET delivers p- and n- FET characteristics as selected by a program signal. Accordingly, a single MOS device technology results and no doping is necessary to build low-operation-power complementary circuits.In Repronano, reconfigurable nanowire transistors shall be built on a silicon on insulator (SOI) basis. The basics steps towards establishing circuit maturity were set in the preceding Repronano funding phase: symmetry of IV characteristics, scaling and performance analysis as well as basic concepts of logical combinatorial circuits. The symmetry adjustment scheme by elastic strain incorporation developed at Repronano allows for scalability of the device. Indeed, up to the submission of this proposal it is the only symmetry method from many groups working on this topic that delivers a circuit maturity.Within the requested project, SOI RFET devices and circuits will be built. In addition to dually gated RFETs, devices with multiple independent gates (MIG) will be demonstrated, further increasing the expressive diversity per device, without affecting on-currents. To lower operation voltages and to enhance device miniaturization surround - high-k / metal gate stacks will be used. To increase on-currents and to decrease the access resistance and capacitances, multiple parallel nanowires will be integrated. This will also allow for accurate capacitance-voltage (CV) characterization with a high precision capacitance loss bridge. 3D finite element device and process simulations will support device verification and predictive design. From electrical measurements and simulation results table models for circuit simulations will be set-up. Unit cells will be designed and novel combinational gates as well as sequential logic circuits will be developed. The impact of fine grain reconfigurability shall be studied and compared to CMOS in terms of delay, area and power consumption. A selection of circuits will be fabricated and demonstrated e.g. a reconfigurable single bit adder. The influence of process variability on the electrical metrics and circuit operation will be studied.