SBIR Phase II: A New Class of Fast Fourier Transforms

该小型企业创新研究(SBIR)第二阶段项目旨在开发用于嵌入式信号处理集成电路的高性能、可编程快速傅立叶变换(FFT)电路。在过去40年中，用于执行并行FFT实现的技术相对保持不变，基本上是基于信号流图及其映射的不同排列。根据摩尔定律，现在主要是通过缩小电路几何结构来实现性能改进。由于集成电路制造的物理限制，预计只有通过更有效的算法实现与先进的集成电路技术相结合，才能实现信号处理的持续改进。该方案基于离散傅立叶变换(DFT)的一种新的矩阵形式，专注于一种完全不同的并行FFT电路体系结构，以实现这一目标。这种新方案的具体优点包括：1)减少对逻辑和存储器资源的要求；2)消耗更少的功率；3)显著增加功能；以及4)由于电路简单、本地连接和结构化，减少了设计、测试和维护工作。该项目的成果是在SBIR第一阶段开发的可行性原型的基础上开发出商业质量的FFT电路。DFT子系统是大量实时通信、雷达、医疗、声学、导航、监视、遥感和机器人检测应用的关键和重要组件，可以说是所有信号处理算法中最突出的。因此，功能更强、效率更高、性能更高的FFT的可用性将显著提高一系列电子产品的效能。这种新的FFT技术的好处将最适合移动无线设备，移动无线设备是电子产品最大和增长最快的市场，因为未来的4G无线协议将基于正交频分复用，这是一种利用FFT的方案。因此，未来的大多数无线设备将使用嵌入式FFT电路。然而，与今天的无线移动设备相比，支持4G通信需求的计算需求将增加约10倍。因此，将需要更高效的FFT集成电路实现，以继续保持移动设备的低成本和低功耗。

This Small Business Innovation Research (SBIR) Phase II project is directed at development of a high performance, programmable fast Fourier transform (FFT) circuit for use in embedded signal processing integrated circuits. Over the last 40 years the technology for executing parallel FFT implementations has remained relatively unchanged, being based essentially on different permutations of the signal flow graph and mappings thereof. Performance improvements are now largely achieved by shrinking circuit geometries according to Moore's Law. Because of the limits imposed by physics of integrated circuit fabrication, it is expected that continued improvement in signal processing will only be achieved with more efficient algorithmic implementations in combination with advanced integrated circuit technologies. This proposal focusses on a radically different architecture for parallel FFT circuits based on a new matrix formulation of the discrete Fourier transform (DFT) to achieve exactly this goal. The specific advantages of this new formulation include: 1) logic and memory resource requirements are reduced; 2) less power is consumed; 3) significant added functionality is accrued; and 4) design, test, and maintenance efforts are diminished because the circuits are simple, locally connected and structured. The outcomes of this project is a commercial quality FFT circuit based on the feasibility prototypes developed during SBIR Phase I.The DFT sub-system is a critical and important component of large number of real-time communications, radar, medical, acoustics, navigation, surveillance, remote sensing, and robotic inspection applications and is arguably the most prominent of all signal processing algorithms. Consequently, the availability of more functional, efficient, and higher performance FFTs will significantly improve the efficacy of a host of electronic products. The benefits of this new FFT technology would be best suited to mobile wireless devices, the largest and fastest growing market for electronic products, because future 4G wireless protocols will be based on orthogonal frequency division multiplexing, which is a scheme that makes use of the FFT. Consequently, most wireless devices of the future will use embedded FFT circuitry. However, the computational demands to support 4G communication requirements will increase by a factor of ~10 compared to today's wireless mobile devices. Therefore, more efficient integrated circuit implementations of FFTs will be required to continue to keep the cost and power usage of mobile appliances low.