CIF: Medium: Analog Architectures for Optimization in Signal Processing

摘要：为获取和处理信号/图像提供最佳性能的现代技术依赖于重复解决数学优化问题，而这些问题的计算成本可能很高。 这项研究涉及将解决此类重要问题的现有技术水平提高几个数量级。 研究人员没有开发适合当前数字计算平台的算法，而是完全脱离当前的研究方向，研究模拟架构来解决这些问题。这些模拟架构在完全开发后，与数字架构相比，在速度和功效方面有可能大幅提升。 该研究项目本质上是多学科的，因为它结合了计算神经科学、信号处理和可重构 VLSI 架构的最新进展。 在其他应用中，这些系统可以减少采集磁共振图像 (MRI) 所需的时间。该项目主要致力于通过模拟动态系统架构解决将均方误差数据保真度项与稀疏性诱导成本函数（例如 L1 范数）相结合的优化程序。 具体来说，该项目包含两个相互交织的线索：电路实现和数学分析。电路实现线程的目标是产生一个模拟电路，该电路能够比最先进的数字解决方案更快地解决重要的优化程序（例如，数万个变量）。 研究人员利用可重构模拟架构的最新进展来实现如此大规模的高效设计。 分析线程包括导出电路收敛时间的界限以及概括架构以包括其他相关信号处理问题。 该研究还涉及应用这种模拟架构作为非线性“滤波器”，它不断对输入的变化做出反应。

Abstract:Modern techniques giving the best performance for acquiring and processing signals/images rely on repeatedly solving mathematical optimization problems which can be computationally expensive. This research involves advancing, by orders of magnitude, the state of the art for solving an important class of these problems. Rather than developing algorithms tailored to current digital computational platform, the investigators depart completely from this current line of research to study analog architectures for solving these problems. These analog architectures, when fully developed, have the potential for dramatic gains in speed and power efficiency over their digital counterparts. This research project is inherently multidisciplinary, as it combines recent advances in computational neuroscience, signal processing, and reconfigurable VLSI architectures. Among other applications, these systems enable reductions in the time needed to acquire a magnetic resonance image (MRI).This project focuses primarily on solving optimization programs combining a mean-squared error data fidelity term with a sparsity inducing cost function (e.g., the L1 norm) via an analog dynamical system architecture. Specifically , the project contains two intertwined threads: circuit implementation and mathematical analysis. The goal of the circuit implementation thread is to produce a analog circuit which solves significant optimization programs (e.g., tens of thousands of variables) substantially faster than state-of-the-art digital solutions. The investigators leverage recent advances in reconfigurable analog architectures to achieve efficient designs at this large scale. The analysis thread includes deriving bounds on the circuit convergence time and generalizing the architecture to include other relevant signal processing problems. The research also involves applying this analog architecture as a nonlinear "filter" which continuously reacts to changes in the input.