SHF: EAGER: Transactional Processors: Exploiting Hardware Transaction Processing for Reliable Computing

SHF：EAGER：事务处理器：利用硬件事务处理实现可靠计算

• 批准号: 0924279
• 负责人: Jie Hu
• 金额: $ 7.5万
• 依托单位: New Jersey Institute of Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-01 至 2010-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0924279&HistoricalAwards=false
• 关键词: SHF; EAGER; Transactional; Processors; Exploiting

With the semiconductor technology entering the nano-scale era, CMOS devices are facing a dramatic increase in vulnerability to transient faults such as soft errors induced by energetic particle strikes. Such soft errors have become a major challenge in designing next generation microprocessors. While techniques for optimizing reliability at low levels can be accurate, they incur significantly high hardware overheads and costly manufacturing processes. The objective of the proposed EAGER proposal is to explore a new flexible processor architecture for highly effective reliable computing by exploiting the semantics of hardware transaction processing. Instead of simply augmenting existing processors for an attainable reliability, the PI proposes to exploit the semantics of transaction processing from database management systems and recent transactional memories for the design and implementation of the transactional processor architecture, where the reliable computing is an inherent property. The transactional processor aims to provide highly effective and flexible transaction-level verification and native supports for recovery from detected errors. The PI will explore the design space of hardware transaction processing and transaction based reliable computing, as well as new programming language constructs to extend current programming languages for writing programs efficiently in transactions. The success of this project may result in design of low-cost reliable computing platforms based on hardware transaction processing. In addition, the proposed activities will provide a unique channel to attract students from under-represented groups and minorities into science and engineering. The PI plans to take advantage of several college and university wide outreach programs to interact with high school students and teachers to motivate them in computer science.

随着半导体技术进入纳米级时代，CMOS器件面临着由高能粒子撞击引起的软误差等瞬态故障的脆弱性急剧增加。这种软误差已经成为设计下一代微处理器的主要挑战。虽然在低水平上优化可靠性的技术可能是准确的，但它们会导致非常高的硬件开销和昂贵的制造过程。所提出的EAGER提案的目标是通过利用硬件事务处理的语义来探索一种新的灵活的处理器体系结构，以实现高效可靠的计算。PI不是简单地增加现有处理器以获得可实现的可靠性，而是建议利用数据库管理系统和最近的事务性内存中的事务处理语义来设计和实现事务性处理器体系结构，其中可靠计算是固有属性。事务处理器旨在提供高效、灵活的事务级验证，并支持从检测到的错误中恢复。PI将探索硬件事务处理和基于事务的可靠计算的设计空间，以及新的编程语言结构，以扩展当前的编程语言，以便在事务中有效地编写程序。本课题的成功为设计基于硬件事务处理的低成本、可靠的计算平台奠定了基础。此外，拟议的活动将提供一个独特的渠道，吸引来自代表性不足的群体和少数民族的学生进入科学和工程领域。PI计划利用几个学院和大学范围内的推广项目，与高中生和教师互动，激励他们学习计算机科学。