Scalable Array Packaging for Optoelectronic Components

光电子元件的阵列封装ERC创新计划A.2pi，Nasser Peyghambarian，亚利桑那州大学Nasser Peyghambarian，加州大学伯克利分校EECS的Connie Chang-Hasnain和ming Wu作为集成接入网络工程研究中心(CIAN)的一部分，该项目将研究可扩展的新型光电子元件封装，例如垂直腔面发射激光器(VCSEL)和可调谐滤光器阵列。这将填补一个主要需求，使专注于新设备的研究小组能够提出适用于系统和试验台的高级表征的组件。这笔资金将支持一名在光电子和光学微电子机械系统(MEMS)方面具有工业实践和创新方面的专业知识和经验的研究工程师。这一职位的特定候选人是S.Patra博士，他在工艺开发和转移方面拥有16年的行业经验。他将带来关键的技能基础，以增强推力III向试验台提供先进概念验证设备的能力，并将研究想法转化为系统架构。在光电子组件行业，封装成本占当前组件组装制造成本的60%至80%，而电子组件仅占10%。要在中国接入网络中部署这里提出的新型光电子组件，必须解决封装成本问题。计划中的策略是，第一，将封装视为设备设计的一部分，而不是事后才想到的；第二，尽可能追求芯片规模的封装。芯片级封装现在被广泛应用于IC和MEMS行业，以减少占地面积和封装成本。该项目包括晶圆级、低成本、密封包装的两个主要组成部分。第一部分包括高速VCSEL阵列的工艺和封装，第二部分包括面内波导阵的制作和封装。第一个项目的挑战是需要多个芯片需要垂直对准，而第二个项目则需要芯片的两个方面都对准。这涵盖了光纤耦合问题中最具挑战性的部分：表面发射2D阵列和边缘发射器件的两个方面的耦合。有了这两种拓扑的解决方案，所开发的结果将很容易扩展到所有光电子器件。Patra博士在这两种类型的封装方面都拥有丰富的行业经验，特别是在光电封装的热、机械和电气设计方面。他的领导将帮助研究生做好准备，将包装考虑纳入设备和材料设计，并在交叉口工作。这一提议的关键科学目标和智力优势是开发一种可扩展的工艺，并提供一个公共平台来组装不同的光电子器件，需要表面法向和面内方向的光学耦合、一系列电信号频率和操作条件。更广泛的影响将是通过提供一个通用的封装平台来有效地弥合光电子器件和系统之间的差距。拟议的工作将促进研究人员在该中心内部和与业界更容易地合作。新工艺将是基本的，可以很容易地扩展到所有边缘发射和表面发射光电子器件。这项工作将对低成本、高产量的光电子器件阵列制造具有重要意义。Cian Photonics试验台的目的是成为第一个针对从基础设备到子系统再到系统的通信系统进行跨学科研究的研究机构。有了帕特拉博士带来的包装技术，推力3号的研究人员发明的设备将能够更积极地参与试验台。由于CIAN赞助REU学生和高中推广计划，这项拟议的工作将为具有现实世界实践和研究经验的本科生和高中生提供更好的准备。

Array Packaging for Optoelectronic ComponentsERC Innovation Program A. 2PI, Nasser Peyghambarian, University of ArizonaConnie Chang-Hasnain and Ming Wu, EECS, University of California, BerkeleyAs part of the Engineering Research Center for Integrated Access Networks (CIAN), this project will investigate scalable and novel packaging for optoelectronic components, e.g. vertical cavity surface emitting laser (VCSEL) and tunable filter arrays. This will fill a major need to enable research groups focusing on novel devices to bring forth components suitable for advanced characterization in systems and testbeds. The funding will support a research engineer with expertise and experience of industrial practice and innovation in optoelectronics and optical micro-electro-mechanical systems (MEMS). The particular candidate identified for this position is Dr. S. Patra, with 16 years of industry experience in process development and transfer. He will bring critical skill base to enhance Thrust III's capability to deliver advance proof-of-concept devices to test beds, and translate research ideas into system architecture.In the optoelectronic components industry, the package cost accounts for 60 to 80% of current manufacturing expenses in component assembly, while it is only 10% in electronic components. To deploy the novel photonic and optoelectronic components proposed here in access networks in CIAN, one must address the packaging cost. The planned strategy is, first, to treat packaging as part of the device design rather than an afterthought; and, second, to pursue chip-scale packaging whenever possible. Chip-scale packaging is now widely employed in IC and MEMS industries to reduce footprint and packaging cost. The project includes two major components of wafer-level, low-cost, hermetic packaging. The first one includes the process and package of a high-speed VCSEL array and the second with in-plane waveguide arrays. The challenge for the first project is the need of multiple chips requiring vertical alignments, while for the second is on requiring alignment of both facets of a chip. This covers the most challenging parts of fiber coupling problems: surface-emitting 2D array and coupling of both facets of edge-emitting devices. With solutions to both topologies, the developed results will be readily extended to all optoelectronic devices. Dr. Patra has significant industrial experiences on both types of packaging, particularly on thermal, mechanical and electric designs of optoelectronic packages. His leadership will help to prepare the graduate students to include packaging considerations into device and material designs and to work at the intersection. The key scientific goals and intellectual merit of this proposal is to develop a scalable process and bring forth a common platform to assemble diverse optoelectronic devices, requiring optical coupling in both surface-normal and in-plane directions, a range of electrical signal frequencies and operating conditions.The broader impacts will be in effectively bridging the gap between optoelectronic devices and systems by providing a universal packaging platform. The proposed work will facilitate researchers to collaborate more readily within the Center and with industry. The new processes will be fundamental and can be readily extended to all edge-emitting and surface-emitting optoelectronic devices. This work will be important for low-cost, high through-put manufacturing of arrays of optoelectronic devices. The purpose of the CIAN Photonics Testbed is to be the first research facility to target cross-disciplinary research on communications systems spanning from fundamental devices to subsystems to systems. With the packaging know-how brought forth by Dr. Patra, the devices invented by Thrust 3 researchers will be able to participate more actively in the testbed. As CIAN sponsors REU students and high school outreach programs, this proposed work will provide better preparation for undergraduate and high school students with real world practices and research experiences.