II-NEW: Implementation of an Architecture Simulation Platform with a Virtualized Real-time Operating System Interface for Kilocore-scale Heterogeneous Embedded Chip MultiProcessors

便携式嵌入式系统对高性能、低功耗的微处理器设计提出了越来越高的要求。这引发了嵌入式处理器行业的范式转变，嵌入式处理器架构师正在永久地改变他们的路线图，将多个内核集成在同一芯片上，以保持指数级的计算速度（延续摩尔定律）。虽然业界的重点是在单个芯片上放置更多的内核，但关键的挑战是优化这些处理器的架构，以满足不同实时操作系统（RTOS）的虚拟化环境中严格的实时约束。此外，这些处理器将在具有零星事件驱动数据的不同应用程序类型上工作。在这样复杂的系统中，最佳性能只能通过共同设计RTOS内核、虚拟化环境和处理器微架构来实现。本研究的目标是开发一个周期精确的仿真平台的微架构的探索未来千核规模的异构嵌入式芯片多处理器（ECMPs），连同一个接口，靴子RTOS的仿真器上，并启用虚拟化的ECMPs。该集成框架是灵活的和模块化的，用于设计各种各样的ECMP和RTOS，灵活地线程化，用于在各种各样的计算平台上快速仿真数千个核心，基于断言和检查点，用于快速重新生成和改变调试所需的复杂触发条件，可即时引导，以减少从上电到仿真的RTOS引导时间，具有深度芯片视觉，可在架构级别更好地观察硅行为，并开源用于非商业用途。RTOS集成环境为架构师和操作系统设计师提供软件接口和库，以在存在不同虚拟化场景和RTOS调度算法的情况下模拟嵌入式应用在不同探索性ECMP上的执行。该项目促进了不同大学和研究机构的计算机架构师、RTOS设计师、计算机辅助设计师和嵌入式应用程序员之间的跨学科研究。该项目的各种教育组成部分将促进大学生参与者之间以团队为基础的研究，学习和教学。

Portable embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. This has triggered a paradigm shift in the embedded processor industry, and embedded processor architects are permanently altering their roadmap to incorporate multiple cores on the same chip to preserve exponential computational speed-up (to continue Moore's law). While the industry focus is on putting higher number of cores on a single chip, the key challenge is to optimally architect these processors to meet stringent real-time constraints in virtualized environments with different real-time operating systems (RTOS). Moreover, these processors will work on diverse application types having sporadic event-driven data. In such complex systems, the optimal performance can only be realized by co-designing the RTOS kernels, the virtualization environment, and the processor micro-architecture. The goal of this research is to develop a cycle-accurate simulation platform for the micro-architectural exploration of future kilocore-scale heterogeneous embedded chip-multiprocessors (ECMPs), together with an interface to boot RTOS-es on the simulator, and enable virtualization on the ECMPs. The integrated framework is flexible and modular for designing a wide variety of ECMPs and RTOS-es, flexibly threaded for fast simulation of thousands of cores on a wide range of computing platforms, assertion-based and check-pointed for quickly regenerating and changing complex trigger conditions required for debugging, instantly-bootable to reduce the RTOS booting time from power-up to simulation, enabled with deep-chip-vision for better observability of silicon behavior at the architectural level, and open-sourced for non-commercial use. The RTOS integration environment provides software interfaces and libraries to the architect and the OS designer to simulate the execution of embedded applications on different exploratory ECMPs, in the presence of different virtualization scenarios and RTOS scheduling algorithms. This project promotes inter-disciplinary research between computer architects, RTOS designers, Computer-Aided Designers, and embedded application programmers at different universities and research institutions. The various education components woven into the project will foster team-based research, learning, and teaching among the university student participants.