II-NEW: Implementation of an Architecture Simulation Platform with a Virtualized Real-time Operating System Interface for Kilocore-scale Heterogeneous Embedded Chip MultiProcessors

便携式嵌入式系统对高性能、低功耗的微处理器设计提出了越来越高的要求。这引发了嵌入式处理器行业的范式转变，嵌入式处理器架构师正在永久地改变他们的路线图，在同一芯片上集成多个内核，以保持指数级的计算速度（继续摩尔定律）。虽然业界关注的焦点是在单个芯片上放置更多的内核，但关键的挑战是优化这些处理器的架构，以满足不同实时操作系统（RTOS）虚拟化环境中严格的实时限制。此外，这些处理器将处理具有零星事件驱动数据的各种应用程序类型。在这种复杂的系统中，只有通过RTOS内核、虚拟化环境和处理器微体系结构的协同设计才能实现最优的性能。本研究的目标是开发一个周期精确的仿真平台，用于未来千核规模异构嵌入式芯片多处理器（ecmp）的微架构探索，以及在模拟器上启动RTOS-es的接口，并在ecmp上实现虚拟化。集成框架灵活且模块化，可用于设计各种ecmp和RTOS-es，灵活的线程用于在各种计算平台上快速模拟数千个内核，基于断言和检查点的快速再生和更改调试所需的复杂触发条件，可立即启动以减少RTOS从上电到模拟的启动时间。支持深度芯片视觉，以便在架构级别上更好地观察硅的行为，并且为非商业用途开源。RTOS集成环境为架构师和操作系统设计人员提供了软件接口和库，以便在不同的虚拟化场景和RTOS调度算法下，在不同的探索性ecmp上模拟嵌入式应用程序的执行。该项目促进了不同大学和研究机构的计算机架构师、RTOS设计人员、计算机辅助设计人员和嵌入式应用程序编程人员之间的跨学科研究。项目中的各种教育组件将促进大学生参与者之间以团队为基础的研究、学习和教学。

Portable embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. This has triggered a paradigm shift in the embedded processor industry, and embedded processor architects are permanently altering their roadmap to incorporate multiple cores on the same chip to preserve exponential computational speed-up (to continue Moore's law). While the industry focus is on putting higher number of cores on a single chip, the key challenge is to optimally architect these processors to meet stringent real-time constraints in virtualized environments with different real-time operating systems (RTOS). Moreover, these processors will work on diverse application types having sporadic event-driven data. In such complex systems, the optimal performance can only be realized by co-designing the RTOS kernels, the virtualization environment, and the processor micro-architecture. The goal of this research is to develop a cycle-accurate simulation platform for the micro-architectural exploration of future kilocore-scale heterogeneous embedded chip-multiprocessors (ECMPs), together with an interface to boot RTOS-es on the simulator, and enable virtualization on the ECMPs. The integrated framework is flexible and modular for designing a wide variety of ECMPs and RTOS-es, flexibly threaded for fast simulation of thousands of cores on a wide range of computing platforms, assertion-based and check-pointed for quickly regenerating and changing complex trigger conditions required for debugging, instantly-bootable to reduce the RTOS booting time from power-up to simulation, enabled with deep-chip-vision for better observability of silicon behavior at the architectural level, and open-sourced for non-commercial use. The RTOS integration environment provides software interfaces and libraries to the architect and the OS designer to simulate the execution of embedded applications on different exploratory ECMPs, in the presence of different virtualization scenarios and RTOS scheduling algorithms. This project promotes inter-disciplinary research between computer architects, RTOS designers, Computer-Aided Designers, and embedded application programmers at different universities and research institutions. The various education components woven into the project will foster team-based research, learning, and teaching among the university student participants.