SHF: Medium: Intelligent and Efficient Data Movement for Multicore Systems

数百核的多核芯片可能很快就会出现。目前的趋势表明，核心将相对简单，芯片上的内存将被划分为每个核心缓存，并且每个缓存将相对较小。此外，芯片将继续受到引脚限制，因此DRAM带宽不会随着核心数量的增加而增加。数据密集型并行软件有可能在多核处理器上运行良好，因为芯片上的缓存总量很大，但需要有效地利用分布式芯片上的缓存。危险在于，多个核心使用的数据将在多个核心的缓存中被复制，从而减少了可以缓存的不同数据的总量；一些核心可能会导致DRAM负载试图访问更多的数据，而其他核心有备用的缓存空间。随着每个DRAM接口的内核数量和芯片上缓存之间的延迟增加，软件很好地管理分布式缓存非常重要。架构师和系统研究人员通过协作的方式来扩展内存接口，以控制数据放置，并实现片上高效的数据移动，从而提供了一个整体的解决方案。具体来说，这项工作提出了数据移动控制（DMC）接口，其中包括对缓存到缓存传输的支持，几条缓存线的批处理，向靠近保存特定数据项的缓存的核心发送消息，以及数据监控。该提案还包括通过互连路由数据的技术，这将为DMC接口提供高性能。如果成功，DMC将帮助数据密集型应用程序避免内存瓶颈，并允许它们在未来的多核处理器上良好运行。全系统模拟器将允许其他研究人员探索智能和高效的数据管理，并使麻省理工学院研究生计算机体系结构课程的研究项目成为可能，教育学生多核计算的挑战。

Multicore chips with hundreds of cores will likely be available soon. Current trends suggest that cores will be relatively simple, that on-chip memory will be partitioned into per-core caches, and that each cache will be relatively small. Furthermore, chips will continue to be pin-limited and therefore DRAM bandwidth won't scale with the number of cores.Parallel software that is data intensive has the potential to run well on multicore processors due to the large total amount of on-chip cache, but requires effective use of the distributed on-chip caches. The dangers are that data used by many cores will be duplicated in many cores' caches, decreasing the total amount of distinct data that can be cached; and that some cores may incur DRAM loads trying to access more data than fits in their caches, while other cores have spare cache space.As the number of cores per DRAM interface and the latencies between caches on a chip increase, it is important for software to manage the distributed caches well. A collaborative approach that involves architects and systems researchers to extend the memory interface to provide control over data placement and enable on-chip efficient data movement provides a holistic solution. Specifically, this work proposes data-movement control (DMC) interface, which includes support for cache-to-cache transfers, batching of several cache lines, sending a message to a core that is close to a cache that holds a particular data item, and data monitoring. The proposal also includes techniques to route data over the interconnect that will provide high performance for the DMC interface.If successful, DMC will help data-intensive applications avoid memory bottlenecks and allow them to run well on future multicore processors. A full-system simulator will allow other researchers to explore intelligent and efficient data management and enable research projects in MIT's graduate computer architecture class, educating students about the challenges of multicore computing.