SHF: Medium: Intelligent and Efficient Data Movement for Multicore Systems

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Multicore chips with hundreds of cores will likely be available soon. Current trends suggest that cores will be relatively simple, that on-chip memory will be partitioned into per-core caches, and that each cache will be relatively small. Furthermore, chips will continue to be pin-limited and therefore DRAM bandwidth won't scale with the number of cores.Parallel software that is data intensive has the potential to run well on multicore processors due to the large total amount of on-chip cache, but requires effective use of the distributed on-chip caches. The dangers are that data used by many cores will be duplicated in many cores' caches, decreasing the total amount of distinct data that can be cached; and that some cores may incur DRAM loads trying to access more data than fits in their caches, while other cores have spare cache space.As the number of cores per DRAM interface and the latencies between caches on a chip increase, it is important for software to manage the distributed caches well. A collaborative approach that involves architects and systems researchers to extend the memory interface to provide control over data placement and enable on-chip efficient data movement provides a holistic solution. Specifically, this work proposes data-movement control (DMC) interface, which includes support for cache-to-cache transfers, batching of several cache lines, sending a message to a core that is close to a cache that holds a particular data item, and data monitoring. The proposal also includes techniques to route data over the interconnect that will provide high performance for the DMC interface.If successful, DMC will help data-intensive applications avoid memory bottlenecks and allow them to run well on future multicore processors. A full-system simulator will allow other researchers to explore intelligent and efficient data management and enable research projects in MIT's graduate computer architecture class, educating students about the challenges of multicore computing.