Collaborative Research: Iterative Downconversion for Broadband Signal Digitization

本研究的目的是研究宽带模数转换的创新频率信道化架构。该方法采用基于图像抑制下转换阶段的空间展开级联的宽带模拟迭代滤波器组。对于n级级联，输入并发分解为2的N-1个连续通道的幂次；每个数字使用转换器时钟为输入奈奎斯特率的1/（2的N-1次方）。所有的下变频器本地振荡器都来源于一个单一的参考级联紧凑，低功率，除以2级。该架构可能允许频率可扩展的分辨率。智力优势：本研究的方法不受传统高速时域采样器的限制，例如对极细时间分辨率的要求。它还避免了当前频域方法中由于需要多个非谐波相关的局部振荡器而产生的主要实现瓶颈。性能限制由于有限的图像抑制，本振杂散，和相位噪声解决了电路级的创新。更广泛的影响：信号数字化能力的创新解决了多个领域技术进步的关键需求，这些领域具有广泛的社会和科学影响，包括计算、通信、传感器、医学和基础科学。独特的架构有望实现新的信号处理密集型实现，利用多分辨率和频率可扩展的设计，在这些领域实现不同的应用。参与这项研究的研究生和本科生将获得高性能数字化仪和信号处理器设计的理论和实验方面的专业知识。这项研究的结果将通过出版物和讨论会加以传播，并将纳入pi教授的研究生课程。

The objective of this research is to investigate innovative frequency channelized architectures for broadband analog-to-digital conversion. The approach employs a broadband analog iterative filter bank based on a spatially unfolded cascade of image-reject down-conversion stages. For an N-stage cascade, the input is concurrently decomposed into 2 to the power of N-1 contiguous channels; each digitized using converters clocked at 1/(2 to the power of N-1) of the input Nyquist rate. All down converter local oscillators are derived from a single reference with a cascade of compact, low power, divide-by-2 stages. The architecture potentially allows for frequency scalable resolution.Intellectual Merit: The approach in this research does not suffer from limitations of traditional high-speed time-domain samplers, such as requirements for extremely fine time resolution. It also avoids a major implementation bottleneck in current frequency-domain approaches arising from the requirement for multiple non-harmonically related local oscillators. Performance limitations due to finite image-rejection, local oscillator spurs, and phase noise are addressed with circuit-level innovations. Broader Impacts: The innovations in signal digitization capability address a critical need for technology advances in multiple areas with broad societal and scientific impact including computing, communications, sensors, medicine, and fundamental science. The unique architecture is expected to enable new signal-processing intensive implementations utilizing multi-resolution and frequency scalable designs with diverse applications in these areas. Graduate and undergraduate students involved in this research will gain expertise in theoretical and experimental aspects of the design of high-performance digitizers and signal processors. The results of this research will be disseminated through publications and seminars and will be incorporated into graduate courses taught by the PIs.