SHF: Small: Exploring Statistical Models to Optimize Hardware and Software under Processor Reliability Constraints

随着技术的扩展以及功率密度的增加，现代处理器遭受潜在的软错误和硬错误。这种多线程处理器的可靠性分析，例如同时多线程（SMT）和芯片多处理器（CMP），其中线程间的资源竞争存在，是一个相对未开发的领域。此外，建模复杂性被两个附加因素加剧：（1）芯片中核的数量增加;以及（2）制造工艺变化带来的异质性。软件明智的，传统的编译器设计的目的是提供高性能和最近的低功耗时，产生的目标代码。然而，随着硬件漏洞的增加，高性能计算程序遭受意外的错误和异常，这可能会通过使用容错技术（如错误检测和检查点）来减轻，但最终仍会损害其性能。除了可靠的硬件平台外，软件设计人员还可以通过生成错误恢复代码来进一步提高系统可靠性。此外，对软件体系结构脆弱性的分析仍处于特设阶段。因此，该项目提出了一个预测框架，通过采用现代统计和机器学习方法来应对上述挑战。该项目的成果包括一个预测框架，该框架指导可靠的软件和硬件优化及其在高性能计算中的应用。更广泛的影响计划包括外联活动和本科生和研究生培训。拟议工作的跨学科性质使学生能够学习不同领域的尖端知识，以扩大他们的培训范围，并提高他们的生产力。来自代表性不足群体的学生将受到鼓励，并优先参加该项目。

With technology scaling coupled with increasing power densities, modern processors suffer from potential soft errors and hard errors. The reliability analysis of such multi-threaded processors, e.g. Simultaneous Multithreading (SMT) and Chip-Multiprocessors (CMP), where inter-thread resource contention exists, is a relatively unexplored area. Furthermore, the modeling complexity is exacerbated by two additional factors: (1) increasing number of cores in a chip; and (2) heterogeneity brought by manufacturing process variation. Software wise, traditional compiler designs are aimed at providing high performance and recently low power when generating object codes. With increasing hardware vulnerabilities, however, high performance computing programs suffer from unexpected errors and exceptions, which might be mitigated by using fault-tolerance techniques such as error detections and check pointing, but still eventually hurt their performance. Apart from a reliable hardware platform, software designers can further improve system reliability by generating error resilient codes. Moreover, analysis of software's architectural vulnerability is still in an ad hoc stage. Therefore, this project proposes a predictive framework to handle the above challenges by employing modern statistical and machine learning methods. The outcomes of this project include a predictive framework which guides for reliable software and hardware optimization and its applications to high performance computing.The broader impact plans include outreach activities and undergraduate and graduate training. The interdisciplinary nature of the proposed work allows students to learn cutting-edge knowledge from different areas to broaden their scope of training as well as to enhance their productivity. Students from the under-represented groups will be encouraged and given priorities for joining the project.