SHF: Small: Exploring Statistical Models to Optimize Hardware and Software under Processor Reliability Constraints

随着技术的扩展和功率密度的增加，现代处理器面临着潜在的软错误和硬错误。同步多线程（SMT）和芯片多处理器（CMP）等多线程处理器存在线程间资源争用，其可靠性分析是一个相对未开发的领域。此外，两个额外的因素加剧了建模的复杂性：(1)芯片中内核数量的增加；(2)制造工艺变化带来的异质性。在软件方面，传统的编译器设计旨在在生成目标代码时提供高性能和低功耗。然而，随着硬件漏洞的增加，高性能计算程序会遭受意想不到的错误和异常，这可能会通过使用容错技术（如错误检测和检查指向）来减轻，但最终仍会损害它们的性能。除了可靠的硬件平台外，软件设计师还可以通过生成抗错误代码来进一步提高系统可靠性。此外，对软件体系结构漏洞的分析仍处于临时阶段。因此，本项目提出了一个预测框架，通过采用现代统计和机器学习方法来处理上述挑战。该项目的成果包括一个预测框架，该框架指导可靠的软件和硬件优化及其在高性能计算中的应用。更广泛的影响计划包括外联活动以及本科生和研究生培训。拟议工作的跨学科性质使学生可以从不同领域学习前沿知识，以扩大他们的培训范围，并提高他们的工作效率。来自弱势群体的学生将被鼓励并优先加入该项目。

With technology scaling coupled with increasing power densities, modern processors suffer from potential soft errors and hard errors. The reliability analysis of such multi-threaded processors, e.g. Simultaneous Multithreading (SMT) and Chip-Multiprocessors (CMP), where inter-thread resource contention exists, is a relatively unexplored area. Furthermore, the modeling complexity is exacerbated by two additional factors: (1) increasing number of cores in a chip; and (2) heterogeneity brought by manufacturing process variation. Software wise, traditional compiler designs are aimed at providing high performance and recently low power when generating object codes. With increasing hardware vulnerabilities, however, high performance computing programs suffer from unexpected errors and exceptions, which might be mitigated by using fault-tolerance techniques such as error detections and check pointing, but still eventually hurt their performance. Apart from a reliable hardware platform, software designers can further improve system reliability by generating error resilient codes. Moreover, analysis of software's architectural vulnerability is still in an ad hoc stage. Therefore, this project proposes a predictive framework to handle the above challenges by employing modern statistical and machine learning methods. The outcomes of this project include a predictive framework which guides for reliable software and hardware optimization and its applications to high performance computing.The broader impact plans include outreach activities and undergraduate and graduate training. The interdisciplinary nature of the proposed work allows students to learn cutting-edge knowledge from different areas to broaden their scope of training as well as to enhance their productivity. Students from the under-represented groups will be encouraged and given priorities for joining the project.