SHF: Small: Leveraging Dynamic Pin Switching to Power Up Dark Silicon and Increase Off-Chip Bandwidth

Dennard Scaling的终结，即随着晶体管越来越小，功率密度不再恒定，导致现代芯片多处理器上大量的非活动或显着低时钟晶体管，以符合功率预算并防止过热。这就是所谓的？黑硅?根据摩尔定律，阻碍扩展的最关键限制之一是什么？未来的法律。此外，片外内存带宽也被证明是一个主要的性能限制因素，特别是对于多核和多核处理器。为了解决这些问题，本项目提出了一种新颖的设计，其中片外引脚可以在供电和传输信号之间动态切换。所提出的动态引脚开关设计的电路实现，只需要对现有的处理器和主板电路进行微小的改变，将被研究。许多问题，包括与DRAM和电力输送网络接口的影响，信号传输和完整性，热问题，以及面积开销将被彻底和仔细地考虑。可切换引脚设计可以通过提供额外的功率来减少暗硅，或者通过增加内存带宽来提高处理器性能。更广泛的影响包括将研究进展纳入本科和研究生教育，以及K-12外展活动。

The end of Dennard Scaling, i.e., as transistors get smaller the power density is no longer constant, has led to a large number of inactive or significantly under-clocked transistors on modern chip multi-processors in order to comply with the power budget and prevent overheating. This so-called ?dark silicon? is one of the most critical constraints that will hinder scaling in accordance with Moore?s Law in the future. Additionally, off-chip memory bandwidth has also proven to be a major performance limiting factor, especially for multi- and many-core processors.To address these concerns, this project proposes a novel design in which off-chip pins can dynamically switch between supplying power and transmitting signals. The circuit implementation for the proposed dynamic pin switching design, requiring only minor changes to existing processor and motherboard circuitry, will be investigated. Many issues including the impact of interfacing with the DRAM and the power delivery network, signal transmission and integrity, thermal issues, and area overhead will be thoroughly and carefully considered. A switchable pin design could be used to mitigate dark silicon by delivering extra power or to boost processor performance by increasing memory bandwidth. The broader impacts include incorporating the research advances into undergraduate and graduate education, as well as K-12 outreach activities.