EAGER: A 32 GHz RISC Computer using 3D and SiGe Emerging Technology

EAGER：使用 3D 和 SiGe 新兴技术的 32 GHz RISC 计算机

• 批准号: 1031440
• 负责人: John McDonald
• 金额: $ 29.98万
• 依托单位: Rensselaer Polytechnic Institute
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-05-01 至 2012-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1031440&HistoricalAwards=false
• 关键词: EAGER; 32; GHz; RISC; Computer

The most important task for scientific computing is to plan the way forward from the current era of multicore microprocessors implemented in deeply submicron CMOS. This has to be done in such a way that performance improvements are guaranteed. Otherwise the escalating costs of fabrication at the nanometer scale will not be sustainable. Multiple core microprocessors face several major problems, not the least of which is codified in Amdahl?s Law. This law states that even if multiple core processors can reduce all parallelizable code to vanishingly small run time, what will remain is serial code. Even relatively small amounts of serial code then limit the gains possible. Consequently it is prudent to pursue a balanced technology approach, in which both parallelizable and serial codes enjoy advantages. For serial code, assuming all instruction level parallelism (ILP) is fully exploited, the only way forward is to execute the serial code on a higher clock rate unit, or HCRU. Since clock rates for CMOS have tended to saturate due to wire scaling problems and excessive heat dissipation, one must look to an alternate three terminal device, but which is compatible with CMOS. This project explores whether the solution lies with an overlooked device, an aggressively scaled SiGe Heterojunction Bipolar Transistor (HBT). The claim for the research to verify is that clock rates of 20-30 GHz are possible at reasonable power levels and densities, but 3D technology is needed to mitigate memory wall problems.

科学计算最重要的任务是规划从当前深亚微米CMOS实现的多核微处理器时代向前发展的道路。 这必须以保证性能改进的方式进行。 否则，纳米级制造成本的不断上升将是不可持续的。 多核微处理器面临着几个主要问题，其中最重要的是在Amdahl编码？s定律。这条定律表明，即使多核处理器可以将所有可并行化的代码减少到非常小的运行时间，剩下的仍然是串行代码。即使是相对少量的串行代码也会限制可能的增益。 因此，追求一种平衡的技术方法是明智的，在这种方法中，并行代码和串行代码都具有优势。对于串行代码，假设所有指令级并行性（ILP）都被充分利用，唯一的方法就是在更高时钟速率的单元（HCRU）上执行串行代码。由于CMOS的时钟速率由于线缩放问题和过度散热而趋于饱和，因此必须寻找与CMOS兼容的替代三端器件。 这个项目探讨了解决方案是否在于一个被忽视的设备，一个积极规模的SiGe异质结双极晶体管（HBT）。 该研究声称，在合理的功率水平和密度下，20-30 GHz的时钟频率是可能的，但需要3D技术来缓解内存墙问题。