CSR: Small: Simulation of Multicore Processors with One (or More) Fast Core(s) Using Wind River SIMICS

CSR：小型：使用 Wind River SIMICS 对具有一个（或多个）快速内核的多核处理器进行仿真

• 批准号: 1216352
• 负责人: John McDonald
• 金额: $ 50万
• 依托单位: Rensselaer Polytechnic Institute
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-09-01 至 2016-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1216352&HistoricalAwards=false
• 关键词: CSR; Small; Simulation; Multicore; Processors

The most important task for scientific computing is to plan the way forward from the current era of multicore microprocessors implemented in deeply submicron CMOS. This has to be done in such a way that performance improvements are guaranteed. Otherwise the escalating costs of fabrication at the nanometer scale will not be sustainable. Heterogeneous multiple core microprocessors face several major problems, not the least of which is codified in Amdahl?s Law, which shows that even relatively small amounts of serial or low-parallelism code can limit the gains that are possible. It is clear that the ultimate way to circumvent this dilemma is to greatly accelerate the serial code using a high clock rate unit (HCRU) core using a ?beyond-CMOS? device approach. Past research suggests that clock rates of 20-30 GHz are possible for many key components using BiCMOS, but 3D technology is needed to mitigate memory wall problems. This research explores a brand new 90nm IBM SiGe HBT (300GHz fT) BiCMOS process to accomplish this goal while trading excess speed for 4X lower power. The strategy will be to redesign certain critical components of a computer in this new process to verify that the same high speed is obtained at a lower power. The second thrust of the project is to verify by high-level simulation that the execution of serial code at a high clock rate will in fact result in the expected improvement in performance. This is to be conducted using the Wind River SIMICS simulation package.

科学计算最重要的任务是规划从当前深亚微米CMOS实现的多核微处理器时代向前发展的道路。 这必须以保证性能改进的方式进行。 否则，纳米级制造成本的不断上升将是不可持续的。 异构多核微处理器面临着几个主要问题，其中最重要的是在Amdahl？s定律，它表明即使是相对少量的串行或低并行代码也会限制可能的收益。 很明显，最终的办法来规避这一困境是大大加快串行代码使用高时钟速率单元（HCRU）的核心使用？超越CMOS？设备方法。 过去的研究表明，对于使用BiCMOS的许多关键组件，20-30 GHz的时钟速率是可能的，但需要3D技术来缓解存储墙问题。这项研究探索了一种全新的90 nm IBM SiGe HBT（300 GHz fT）BiCMOS工艺来实现这一目标，同时以4倍的低功耗换取额外的速度。该战略将是重新设计计算机的某些关键部件，以验证在较低的功率下获得相同的高速。 该项目的第二个目标是通过高级仿真来验证以高时钟速率执行串行代码实际上会导致预期的性能改善。 这将使用Wind River SIMICS模拟包进行。