EAGER: The Exploration of Memory Hierarchy Design and Optimization for Multi-core Systems

EAGER：多核系统内存层次设计与优化的探索

• 批准号: 1055290
• 负责人: Meilin Liu
• 金额: $ 19.06万
• 依托单位: Wright State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-09-01 至 2013-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1055290&HistoricalAwards=false
• 关键词: EAGER; Exploration; Memory; Hierarchy; Design

Recently, there has been a growing disparity between processor and memory speeds; this disparity is called the ?memory wall? problem. Memory performance has a dominating effect on overall system performance, especially for the data-dominated applications. Also, memory usually occupies half of the surface of the integrated chip of the multi-core system; the total amount of memory required is also a main contributor of the manufacturing cost and the chip size of the multi-core CPU. Memory also dictates the power consumption, since memories and buses consume large quantities of energy. The ?memory wall? problem becomes even more serious when throughput in the processor part is propelled by multi-core architectures.In this proposal, the PI is carrying out research to address the ?memory wall? problem and to develop potentially transformative approaches for memory hierarchy design and configuration in multi-core systems. Different memory architectures can lead to different solutions with different costs and with different performances. Memory size, memory configuration, and memory architecture will be optimized simultaneously for multi-core architectures in order to effectively and efficiently achieve higher performance.

最近，处理器和内存速度之间的差距越来越大;这种差距被称为？记忆墙问题.内存性能对整个系统的性能有着决定性的影响，特别是对于数据占主导地位的应用程序。此外，内存通常占据多核系统集成芯片表面的一半;所需的内存总量也是多核CPU制造成本和芯片尺寸的主要贡献者。存储器还决定了功耗，因为存储器和总线消耗大量的能量。什么？记忆墙问题变得更加严重时，在处理器部分的吞吐量是由多核架构推动。在这项建议中，PI正在进行研究，以解决？记忆墙问题，并开发潜在的变革性的方法，在多核系统中的存储器层次结构的设计和配置。不同的存储器架构可以导致具有不同成本和不同性能的不同解决方案。内存大小、内存配置和内存架构将同时针对多核架构进行优化，以便有效和高效地实现更高的性能。