SHF: Small: Measurement and Analysis of Regional Process Variations using Existing and Minimally Invasive On-Chip Embedded Resources

SHF：小型：使用现有和微创片上嵌入式资源测量和分析区域工艺变化

• 批准号: 1118025
• 负责人: James Plusquellic
• 金额: $ 30万
• 依托单位: University of New Mexico
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-07-01 至 2016-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1118025&HistoricalAwards=false
• 关键词: SHF; Small; Measurement; Analysis; Regional

Precisely controlling the physical parameters of an integrated circuit (IC) fabrication process is becoming more challenging in advanced technology nodes. This lack of control manifests as increasing levels of variations in power and delay in product chips. Unfortunately, regional or within-die variations have increased sharply in recent technologies, and many are dependent on the context of the design layout region. The traditional methods of tracking process variations, e.g., those that utilize scribe line test structures, have become increasingly less effective for predicting power and delay variations within chips that they are adjacent to. This has driven the need for embedded test structures, i.e., those incorporated directly into the product IC. This research is designed to address the deficiencies in the current state-of-the-art of embedded test structure design by focusing on designs that are truly embedded and leverage as much of the existing chip infrastructure as possible. For example, power islands will be investigated as a means of obtaining regional leakage variations and non-invasive modifications to the scan chain architecture will be investigated as a means of measuring regional delay and power variations.A key emphasis of the proposed work is to improve the correlation of embedded test structure measurements with actual chip parameters, e.g., by developing test and measurements techniques that are carried out under actual operating conditions. Both graduate and undergraduate students will participate in the design and test of fabricated chips, which will enhance their educational experience thus preparing them for a more technologically educated workforce for the IC industry.

精确控制集成电路（IC）制造过程的物理参数在高级技术节点中变得越来越具有挑战性。缺乏控制表明，产品芯片的功率和延迟的变化水平不断提高。不幸的是，最近的技术中的区域或DIE内部变化急剧增加，许多差异取决于设计布局区域的上下文。传统的跟踪过程变化的方法，例如那些利用Scribe Line测试结构的方法，对于预测与其相邻的芯片内的功率和延迟变化的有效性变得越来越降低。这促使需要嵌入的测试结构，即直接掺入产品IC的测试结构。这项研究旨在通过专注于真正嵌入的设计并利用尽可能多的现有芯片基础架构来解决嵌入式测试结构设计当前最新的缺陷。例如，将研究电源岛作为获得区域泄漏变化的一种手段以及对扫描链结构的非侵入性修改，将研究作为衡量区域延迟和功率变化的一种手段。拟议工作的关键强调是为了改善嵌入式测试的测试和测试的嵌入式测试条件，并逐步衡量了该测试，并逐步衡量了该测试，并逐步衡量了该测试。研究生和本科生都将参与制造筹码的设计和测试，这将增强他们的教育经验，从而为他们为IC行业提供更具技术教育的劳动力做好准备。