MRI: Development of a Highly Scalable and Reconfigurable Testbed in Support of Future Many-Core and System-on-Chip Research and Design Exploration

提案编号：11- 26688 PI（s）：Yang，Mei Jiang，Yingtao; Qi，Minghao机构：内华达州大学，拉斯维加斯标题：MRI/开发：支持未来众核和片上系统研究与设计探索的高度可扩展和可重构测试床项目建议：该项目来自EPSCoR状态，旨在开发一个高度可扩展和可重构的基于多板的测试床，可以仿真和验证未来大规模众核和片上系统系统，增强多核系统设计的未来。具体来说，该测试平台可以高效地仿真片上网络（NoC）和全系统级别的所有功能。拟议的工作建立了一个高性能，多核测试平台在内华达州，使以下研究项目的片上系统设计：-仿真新的计算机架构设计，-设计空间探索的NoC为基础的众核设计，-仿真混合光电NoC架构，和-交通建模和基准development.The工作的目的是开发一个灵活的测试平台的NoC架构被视为未来的多处理器设计的关键。近年来，计算机架构的加速已经开始完全依赖于多核范式，而不是更快的内核。有一个普遍的共识是，这些许多核心必须通过功能正确，节能，可靠的片上通信架构，现在广泛称为片上网络连接在一起。这种类型的测试床对计算机行业的经济活力至关重要。更广泛的影响：这种仪器应该为教师和研究生提供一个独特的研究设施，以进行NoC架构技术和教育的研究。该试验台将通过网络基础设施远程访问机制提供给全国各地的研究人员。拟议的试验台提高了博士学位。在EPSCoR状态下生产并固化UNLV？在NoC体系结构研究中的地位。

Proposal #: 11-26688PI(s): Yang, Mei Jiang, Yingtao; Qi, MinghaoInstitution: University of Nevada, Las VegasTitle: MRI/Dev.: Highly Scalable and Reconfigurable Testbed in Support of Future Many-Core and System-on-Chip Research and Design ExplorationProject Proposed:This project from an EPSCoR state, aiming to develop a highly scalable and reconfigurable multi-board-based testbed which can emulate and validate future large-scale many-core and system-on-chip systems, enhances the future for design of multi-core systems. Specifically, this testbed efficiently and effectively emulates all the functionalities that are perceived at both the network-on-chip (NoC) and the full-system levels. The proposed work establishes a high performance, multi-core testbed in Nevada, enabling the following research projects in system-on-chip design:- Emulation of new computer architecture designs,- Design space exploration for NoC-based many-core designs,- Emulation of hybrid photonic-electronic NoC architectures, and- Traffic modeling and benchmark development.The work aims to develop a flexible testbed for NoC architectures seen to be key to the future of multiprocessor design. In recent years, computer architecture speed-ups have begun to rely exclusively on multi-core paradigms instead of faster cores. There is a general consensus that these many cores have to be linked together through a functionally correct, power-efficient, and reliable on-chip communication architecture, now widely known as network-on-chip. Testbeds of this type are critical to economic vitality in the computer industry.Broader Impacts: This instrumentation should provide a unique research facility for faculty and graduate students to conduct research on NoC architecture technology and education. The testbed will be made available to researchers around the country through a cyberinfrastructure remote access mechanism. The proposed testbed enhances Ph.D. production in an EPSCoR state and solidifies UNLV?s position in NoC architecture research.