MRI: Development of a Highly Scalable and Reconfigurable Testbed in Support of Future Many-Core and System-on-Chip Research and Design Exploration

提案#：11-26688PI(S)：杨美江应涛；齐明浩研究所：内华达大学拉斯维加斯分校题目：磁共振/开发：支持未来多核和片上系统研究与设计探索的高可扩展可重构测试床项目建议：该项目从EPSCoR状态出发，旨在开发一个高度可扩展和可重构的多板测试平台，可以仿真和验证未来大规模多核和系统级芯片系统，增强多核系统设计的未来。具体地说，该测试床高效且有效地模拟了片上网络(NoC)和全系统级别的所有功能。这项工作在内华达州建立了一个高性能的多核测试平台，使得以下片上系统设计研究项目成为可能：-新计算机体系结构设计的仿真，-基于NoC的多核设计的设计空间探索，-光子-电子混合NoC体系结构的仿真，以及-流量建模和基准测试开发。工作旨在为被视为未来多处理器设计关键的NoC体系结构开发一个灵活的测试平台。近年来，计算机体系结构的加速已经开始完全依赖多核范例，而不是更快的内核。人们普遍认为，这些核心必须通过功能正确、高能效和可靠的片上通信体系结构连接在一起，这种体系结构现在被广泛称为片上网络。这种类型的试验台对计算机行业的经济活力至关重要。广泛的影响：这种仪器应该为教职员工和研究生提供一个独特的研究设施，以进行关于NOC架构技术和教育的研究。试验床将通过网络基础设施远程访问机制向全国各地的研究人员提供。拟议的试验台增强了EPSCoR状态下的博士生产，并巩固了UNLV？S在NoC体系结构研究中的地位。

Proposal #: 11-26688PI(s): Yang, Mei Jiang, Yingtao; Qi, MinghaoInstitution: University of Nevada, Las VegasTitle: MRI/Dev.: Highly Scalable and Reconfigurable Testbed in Support of Future Many-Core and System-on-Chip Research and Design ExplorationProject Proposed:This project from an EPSCoR state, aiming to develop a highly scalable and reconfigurable multi-board-based testbed which can emulate and validate future large-scale many-core and system-on-chip systems, enhances the future for design of multi-core systems. Specifically, this testbed efficiently and effectively emulates all the functionalities that are perceived at both the network-on-chip (NoC) and the full-system levels. The proposed work establishes a high performance, multi-core testbed in Nevada, enabling the following research projects in system-on-chip design:- Emulation of new computer architecture designs,- Design space exploration for NoC-based many-core designs,- Emulation of hybrid photonic-electronic NoC architectures, and- Traffic modeling and benchmark development.The work aims to develop a flexible testbed for NoC architectures seen to be key to the future of multiprocessor design. In recent years, computer architecture speed-ups have begun to rely exclusively on multi-core paradigms instead of faster cores. There is a general consensus that these many cores have to be linked together through a functionally correct, power-efficient, and reliable on-chip communication architecture, now widely known as network-on-chip. Testbeds of this type are critical to economic vitality in the computer industry.Broader Impacts: This instrumentation should provide a unique research facility for faculty and graduate students to conduct research on NoC architecture technology and education. The testbed will be made available to researchers around the country through a cyberinfrastructure remote access mechanism. The proposed testbed enhances Ph.D. production in an EPSCoR state and solidifies UNLV?s position in NoC architecture research.