MRI: Development of a Highly Scalable and Reconfigurable Testbed in Support of Future Many-Core and System-on-Chip Research and Design Exploration

项目编号：11-26688PI(s)：杨，蒋梅，英涛；齐明浩机构：内华达大学拉斯维加斯分校职称：MRI/Dev；项目建议：该项目来自EPSCoR状态，旨在开发一个高度可扩展和可重构的基于多板的试验台，可以模拟和验证未来的大规模多核和片上系统，增强多核系统设计的未来。具体来说，该测试平台可以高效地模拟在片上网络（NoC）和全系统级别上感知到的所有功能。提议的工作在内华达州建立了一个高性能，多核测试平台，使系统芯片设计的以下研究项目成为可能：-新计算机体系结构设计的仿真，-基于NoC的多核设计的设计空间探索，-混合光子-电子NoC体系结构的仿真，以及-流量建模和基准开发。这项工作旨在为NoC架构开发一个灵活的测试平台，这被认为是未来多处理器设计的关键。近年来，计算机架构加速已经开始完全依赖于多核范式，而不是更快的核心。普遍的共识是，这些核心必须通过功能正确、节能且可靠的片上通信架构（现在被广泛称为片上网络）连接在一起。这种类型的试验台对计算机行业的经济活力至关重要。更广泛的影响：该仪器应该为教师和研究生提供一个独特的研究设施，以进行NoC架构技术和教育的研究。该试验台将通过网络基础设施远程访问机制提供给全国各地的研究人员。该试验台提高了EPSCoR状态下的博士产量，并固化了UNLV？中国在NoC架构研究中的地位。

Proposal #: 11-26688PI(s): Yang, Mei Jiang, Yingtao; Qi, MinghaoInstitution: University of Nevada, Las VegasTitle: MRI/Dev.: Highly Scalable and Reconfigurable Testbed in Support of Future Many-Core and System-on-Chip Research and Design ExplorationProject Proposed:This project from an EPSCoR state, aiming to develop a highly scalable and reconfigurable multi-board-based testbed which can emulate and validate future large-scale many-core and system-on-chip systems, enhances the future for design of multi-core systems. Specifically, this testbed efficiently and effectively emulates all the functionalities that are perceived at both the network-on-chip (NoC) and the full-system levels. The proposed work establishes a high performance, multi-core testbed in Nevada, enabling the following research projects in system-on-chip design:- Emulation of new computer architecture designs,- Design space exploration for NoC-based many-core designs,- Emulation of hybrid photonic-electronic NoC architectures, and- Traffic modeling and benchmark development.The work aims to develop a flexible testbed for NoC architectures seen to be key to the future of multiprocessor design. In recent years, computer architecture speed-ups have begun to rely exclusively on multi-core paradigms instead of faster cores. There is a general consensus that these many cores have to be linked together through a functionally correct, power-efficient, and reliable on-chip communication architecture, now widely known as network-on-chip. Testbeds of this type are critical to economic vitality in the computer industry.Broader Impacts: This instrumentation should provide a unique research facility for faculty and graduate students to conduct research on NoC architecture technology and education. The testbed will be made available to researchers around the country through a cyberinfrastructure remote access mechanism. The proposed testbed enhances Ph.D. production in an EPSCoR state and solidifies UNLV?s position in NoC architecture research.