SGER: An Energy-Efficient and Scalable Network-on-Chips Architecture

方案：ECS-0549181PI：美杨安高效节能和可扩展的片上网络架构VLSI技术的进步将很快使单个芯片包含超过10亿个晶体管，这意味着将大量复杂的处理单元（如CPU、DSP、多媒体处理器）集成到一个封装芯片中。在这些新系统中，通信资源受到大量计算资源的竞争。遵循以通信为中心的设计风格，提出了片上网络（NoC）来减轻这些密集集成芯片的复杂通信需求。在本提案中，我们研究了一种新型节能且高度可扩展的NoC架构，以解决以下重要问题：可扩展性，能源效率和可重构性。具体而言，我们将(i)为NoC设计和分析一个可定制的递归对角环（RDT）架构，（ii）研究各种可重构组件在可扩展性和路由性能方面对提议的NoC架构性能的影响，（iii）研究与提议的NoC架构相关的节能通信协议，以及（iv）开发一个通用仿真框架来评估提议的NoC架构和相关交换。路由和重新配置方案。提出的研究的智力优点包括：(i)将RDT结构（一种新颖的并行架构）应用于NoC的设计；（ii）开发一个通用的仿真框架，这将有利于在这一新兴领域进行研究的研究团体；（iii）研究通用的可重构NoC架构，这将有助于理解与NoC范式相关的基本问题。建议研究的广泛影响包括改善现有课程，以及开发新课程，以加强我们的电气和计算机工程课程，并让本科生参与建议的研究工作。

Proposal: ECS-0549181PI: Mei YangAn Energy-Efficient and Scalable Network-on-Chips ArchitectureAdvances in VLSI technology will soon allow a single chip to contain more than one billion transistors, indicating that a large number of complex processing units (such as CPU, DSP, multimedia processor) shall be integrated into one packaged chip. In these new systems, communication resources are competed by the vast volume of computing resources. Following a communication-centric design style, Network-on-Chip (NoC) was proposed to mitigate the complex communication requirements for these densely integrated chips. In this proposal, we investigate a novel energy-efficient and highly scalable NoC architecture to address the following important problems: scalability, energy efficiency and reconfigurability. In detail, we will (i) design and analyze a customizable Recursive Diagonal Torus (RDT) architecture for NoC, (ii) investigate the effects of various reconfigurable components on the performance of the proposed NoC architecture in terms of scalability and routing performance, (iii) investigate the energy-efficient communication protocols pertaining to the proposed NoC architecture, and (iv) develop a generic simulation framework to evaluate the proposed NoC architecture and related switching, routing, and reconfiguration schemes. The intellectual merits of the proposed research include: (i) applying the RDT structure, a novel parallel architecture, to the design of NoC, (ii) developing a generic simulation framework that will benefit the research communities pursuing research in this emerging area, and (iii) investigating the generic reconfigurable NoC architecture that will help understanding of the fundamental issues related to the NoC paradigm.The broader impacts of the proposed research include improving existing courses as well as developing new ones to enhance our electrical and computer engineering curriculum, and involving undergraduates in the proposed research work.