SGER: An Energy-Efficient and Scalable Network-on-Chips Architecture

建议：ECS-0549181PI：梅艳安节能可扩展片上网络体系结构VLSI技术的进步将很快使单个芯片包含超过10亿个晶体管，这意味着大量复杂的处理单元(如CPU、DSP、多媒体处理器)将集成到一个封装芯片中。在这些新系统中，通信资源被海量的计算资源竞争。遵循以通信为中心的设计风格，片上网络(NoC)被提出以缓解这些密集集成芯片的复杂通信需求。在该方案中，我们研究了一种新的节能和高度可扩展的片上网络体系结构来解决以下重要问题：可伸缩性、能源效率和可重构性。具体而言，我们将(I)设计和分析一种可定制的NoC递归对角环(RDT)体系结构，(Ii)从可扩展性和路由性能方面研究各种可重构组件对所提出的NoC体系结构性能的影响，(Iii)研究与所提出的NoC体系结构相关的节能通信协议，以及(Iv)开发一个通用的仿真框架来评估所提出的NoC体系结构以及相关的交换、路由和重新配置方案。这项研究的学术价值包括：(I)将RDT结构，一种新颖的并行体系结构，应用到片上网络的设计中；(Ii)开发一个通用的仿真框架，将有益于在这一新兴领域进行研究的研究社区；以及(Iii)研究通用的可重构的片上网络架构，将有助于理解与片上网络范例相关的基本问题。拟议研究的更广泛的影响包括改进现有课程以及开发新的课程来增强我们的电气和计算机工程课程，以及让本科生参与拟议的研究工作。

Proposal: ECS-0549181PI: Mei YangAn Energy-Efficient and Scalable Network-on-Chips ArchitectureAdvances in VLSI technology will soon allow a single chip to contain more than one billion transistors, indicating that a large number of complex processing units (such as CPU, DSP, multimedia processor) shall be integrated into one packaged chip. In these new systems, communication resources are competed by the vast volume of computing resources. Following a communication-centric design style, Network-on-Chip (NoC) was proposed to mitigate the complex communication requirements for these densely integrated chips. In this proposal, we investigate a novel energy-efficient and highly scalable NoC architecture to address the following important problems: scalability, energy efficiency and reconfigurability. In detail, we will (i) design and analyze a customizable Recursive Diagonal Torus (RDT) architecture for NoC, (ii) investigate the effects of various reconfigurable components on the performance of the proposed NoC architecture in terms of scalability and routing performance, (iii) investigate the energy-efficient communication protocols pertaining to the proposed NoC architecture, and (iv) develop a generic simulation framework to evaluate the proposed NoC architecture and related switching, routing, and reconfiguration schemes. The intellectual merits of the proposed research include: (i) applying the RDT structure, a novel parallel architecture, to the design of NoC, (ii) developing a generic simulation framework that will benefit the research communities pursuing research in this emerging area, and (iii) investigating the generic reconfigurable NoC architecture that will help understanding of the fundamental issues related to the NoC paradigm.The broader impacts of the proposed research include improving existing courses as well as developing new ones to enhance our electrical and computer engineering curriculum, and involving undergraduates in the proposed research work.