SBIR Phase II: Integrated Circuit Yield and Quality Improvement thru Test Data Analysis

这个小型企业创新研究（SBIR）第二阶段项目开发了一种自动化的、基于软件的分析方法，通过从测试测量数据中提取信息来提高集成电路（ic）的产量和质量。从测试数据中获得可操作的信息是一项具有挑战性的任务，因为缺乏能够自动将从故障ic中获得的测试测量数据与其物理ic设计描述（即布局）相关联的软件。最大限度地提取知识是通过一种新的基于软件的诊断技术来完成的，该技术结合了逻辑和布局描述，以及测量的测试数据，以在纳米尺度上识别非工作ic内缺陷的精确位置和类型。该项目还开发了基于软件的统计方法，用于在失败的集成电路中发现缺陷的共性。改进的诊断和通用性分析的结合意味着可以快速找到故障的根本原因，并将其传递给设计人员、过程工程师和测试工程师，以指导补救措施的选择和部署。该项目的更广泛的影响/商业潜力集中在继续推进美国半导体产业，这对国土安全和整个社会的普遍进步至关重要。为集成电路（IC）生产商提供基于每个设计的测试数据分析具有重要的商业机会，可以通过制造测试的反馈快速提高产量和质量。潜在的影响是巨大的，因为具体的、相关的信息反馈给设计师和制造商，关于ic如何以及为什么失败。芯片设计师将利用这些信息来改进设计规则，以生产高产量和超可靠的集成电路。芯片制造商将利用这些信息来微调他们的制造工艺，以最大限度地提高产量和性能，并优化他们的测试方法，以确保质量满足客户需求。预计这项技术还将刺激进一步的研究，并扩大大学的研究范围。

This Small Business Innovation Research (SBIR) Phase II project develops an automated, software-based analysis methodology that enables yield and quality improvement of integrated circuits (ICs) through information extraction from test measurement data. Deriving actionable information from test data is a challenging task due to lack of software that automatically correlates test measurement data obtained from failing ICs and their physical IC-design description (i.e., the layout). Maximizing knowledge extraction is accomplished by a new software-based diagnosis technique that uses in conjunction the logical and layout descriptions, in addition to the measured test data, to identify at the nanometer scale, the precise location and type of defects within non-working ICs. The project also develops software-based statistical methods that find commonalities among the defects characterized within failing ICs. The combination of improved diagnosis and commonality analyses means that the root-causes for failure can be quickly found and passed on to designers, process engineers, and test engineers to guide remedy selection and deployment.The broader impact/commercial potential of this project centers on continuing the advancement of the US semiconductor industry which is vital to both Homeland Security and the general advancement of society as a whole. There is significant commercial opportunity in supplying test data analysis on a per-design basis to Integrated Circuit (IC) producers that enables rapid improvement in yield and quality through feedback from manufacturing testing. The potential impact is tremendous since specific, pertinent information is fed back to both designers and manufacturers about how and why ICs fail. Chip designers will use this information to improve design rules for producing high-yielding and ultra-reliable ICs. Chip manufacturers will use this information to fine-tune their fabrication processes to maximize yield and performance, and optimize their test methodologies to ensure quality meets customer demands. It is also anticipated that this technology will also spur further research and broaden the scope of research in universities.