SBIR Phase I: On Demand Verification for Analog Integrated Circuits

这个小型企业创新研究第一阶段项目提出了一个按需验证（ODV）设施模拟/混合信号应用（A/MS）专用集成电路（ASIC）。该技术创新是一个基于云的虚拟化验证平台，支持集成电路设计中心的A/MS ASIC验证的各个方面，包括行为建模、测试台管理、仿真规划、仿真农业和数据挖掘。 所提出的ODV系统通过利用云计算资源来扩展ASIC复杂性和设计人员扩展。 更重要的是，一旦验证任务完成，拟议的验证资源可以按比例缩小，为小型设计中心创造机会，以创建具有竞争力的设计操作成本结构的高质量设计。 最初的概念验证设计系统将配备开源EDA设计，建模和验证软件工具。 拟议验证平台固有的模块性还将支持ODV设施的用户安装一流的商业合作伙伴软件解决方案及其在ASIC验证活动中的使用。该项目的更广泛影响/商业潜力是通过减少A/MS设计验证周期时间，提高首次通过设计成功率和缩短上市时间来提高美国半导体行业的竞争力。 A/MS ASIC设计的复杂性一直在积极地追随摩尔？的法律，但在设计验证的创新没有。 在现有的EDA许可模式下，小型无晶圆厂模拟设计中心在复杂的设计创作中尤其难以竞争。 例如，为一个小型设计团队配备适当的验证和分析工具，在财政上相当于将工作人员增加四倍。 这项研究工作的结果将通过提供可扩展的验证服务来降低小型和新兴公司的进入和创新障碍，而无需额外的软件许可成本和基础设施开销的繁重负担。 此外，ODV系统通过基于云的平台使市场参与者之间能够进行更多的协作创新。这将使现有的半导体市场参与者受益，并为新的参与者打开大门。

This Small Business Innovation Research Phase I project proposes an on-demand verification (ODV) facility for analog / mixed-signal application (A/MS) specific integrated circuits (ASICs). The technology innovation is a virtualized cloud-based verification platform that supports all aspects of A/MS ASIC verification for integrated circuit design centers, including behavioral modeling, test bench management, simulation planning, simulation farming, and data mining. The proposed ODV system scales with ASIC complexity and design staff expansion by leveraging cloud computing resources. More importantly, the proposed verification resources can be scaled down once verification tasks are complete, creating opportunities for small design centers to create high quality designs with competitive cost structure for design operations. The initial proof-of-concept design system will be equipped with open source EDA design, modeling, and verification software tools. The modularity inherent in the proposed verification platform will also support the installation of best-in-class commercial partner software solutions and their use in ASIC verification activities by subscribers to the ODV facility.The broader impact/commercial potential of this project is to improve the competitiveness of U.S. semiconductor industry by reducing A/MS design verification cycle time, improving first pass design success and reducing time-to-market. The complexity of A/MS ASIC design has aggressively followed Moore?s law, but innovations in design verification have not. Small, fabless analog design centers in particular struggle to compete in complex design creation given the existing EDA licensing model. Equipping a small design team with the proper verification and analysis tools, for example, is financially equivalent to quadrupling the staff. The results of this research work will lower barriers to entry and innovation for small and emerging companies by providing a scalable verification service without the onerous burden of additional software licensing costs and infrastructure overhead. In addition, the ODV system enables more collaborative innovation among the market players through a cloud-based platform. This would materially benefit the existing semiconductor market participants and open the door for new participants.