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SHF:CSR:Small:Improving Processor Efficiency with Prediction

SHF:CSR:Small:Improving Processor Efficiency with Prediction
SHF:CSR:Small:通过预测提高处理器效率
批准号:
1216604
负责人:
Daniel Jimenez
金额:
$35.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2012
资助国家:
美国
项目状态:
已结题
起止时间:
2012-08-01 至 2013-04-30

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中文摘要
翻译
几十年来,计算机变得越来越快。 这种性能上的改进大部分是由于摩尔定律,即,可以集成到单个微芯片中的设备数量的快速增长。 然而,利用由摩尔定律提供的不断增长的资源的技术通常是低效和浪费的。 这个项目认真研究了用于提高性能的技术,展示了如何减少资源消耗的技术。 改进的结构使用从计算机科学的其他领域借来的技术来预测计算机的近期资源使用情况,以便更好地分配这些资源。 这些预测技术使系统的能效和性能更高。能效和性能的提高具有广泛的影响,从提高移动的设备的电池寿命到降低数据中心的能源成本和环境影响。该项目将让大学生参与研究,帮助培训下一代技术工作者和教育工作者,该项目应用微结构预测技术,回收浪费的资源,从而提高微处理器的效率。 该项目探讨了以下减少预测浪费的机会:1)将高度准确的分支预测技术应用于其他领域,如缓存,2)使用混合模拟/数字电路实现,以提高预测精度,同时减少预测器本身的浪费,以及3)开发一套新的置信度估计技术,并考虑在各种微架构优化中使用它们。
英文摘要
For several decades, computers have been getting faster. Much of this improvement in performance is due to Moore's Law, i.e., the rapid growth in the number of devices that can be integrated into a single microchip. However, techniques that exploit the growing resources provided by Moore's Law are often inefficient and wasteful. This project takes a hard look at techniques used to improve performance, showing how resource-hungry techniques can be made less wasteful. The improved structures use techniques borrowed from other areas of Computer Science to predict the near-term resource usage of the computer to do a better job of allocating those resources. These prediction techniques result in a system that is both more power efficient and better performing.Improvements in power efficiency and performance have a wide-ranging impact, from improving battery life in mobile devices to reducing energy costs and environmental impact of data centers. The project will involve university students in research, helping to train the next generation of technology workers and educators.This project applies microarchitectural prediction techniques to recover wasted resources and thus improve the efficiency of microprocessors. The project explores the following opportunities for reducing waste with prediction: 1) applying highly accurate branch prediction techniques to other domains such as caches, 2) using mixed analog/digital circuit implementations to improve prediction accuracy while reducing waste in the predictor itself, and 3) developing a set of new confidence estimation techniques and considering their use in a variety of microarchitectural optimizations.
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会议论文
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