EAGER: Deep Learning for Microarchitectural Prediction

计算机程序通常具有高度可预测的行为。 微处理器使用预测器来提高程序的性能和效率。程序所做的决策通常可以很好地预测，数据使用模式可以预测，以提高系统的效率和性能。然而，不正确的预测可能会导致性能低下或失去提高效率的机会。该项目提出使用深度学习来改善微处理器中的预测。深度学习是一种技术，已被用于在大型计算系统中改进计算机视觉和其他模式识别任务，但到目前为止，它还没有在改进微处理器的非常小的规模和严格的时间裕度上应用。该项目可能会改进微处理器，并为计算机科学领域代表性不足的群体提供教育、指导和职业机会。PI将把研究纳入课堂教学。的博士通过该项目培训的学生将加强工业和学术工作队伍。PI将继续招募女性和少数民族研究生参加该项目的研究计划。对代表性不足的群体的拓展将包括PI领导和参与针对女性和少数民族研究生的CRA-W指导研讨会。拟议研究的目标是利用深度学习来设计新的微架构预测器，这些预测器能够利用以前未开发的程序行为可预测性水平来提高性能，功率和能量。深度神经网络将被用于大大提高微架构预测器的准确性。这个项目将首先探索延迟容忍缓存位置预测器，然后转移到具有更严格时序约束的控制流预测。建议的预测因素将在各种背景下进行评估，这些背景代表从移动的电话到网络中心的现代工作负载。这项研究具有很高的风险，因为还没有开发出在亚纳秒级运行的深度神经网络。然而，由于提高性能的巨大潜力，该研究提供了高回报。成果将通过学生的论文和学位论文以及在顶级建筑场所的出版物来体现。

Computer programs often have highly predictable behavior. Microprocessors use predictors to improve program performance and efficiency. Decisions made by a program can often be predicted with good accuracy, and patterns of data usage can be predicted to improve system efficiency and performance. However, incorrect predictions can lead to poor performance or lost opportunities for improving efficiency. This project proposes to use deep learning to improve prediction in microprocessors. Deep learning is a technology that has been used to improve computer vision and other pattern recognition tasks in large computing systems, but so far it has not been applied at the very small scale and tight timing margins of improving microprocessors. The project will likely result in improved microprocessors, as well as educational, mentoring, and career opportunities for under-represented groups in computer science. The PI will incorporate the research into classroom teaching. The Ph.D. students trained through this project will enhance industrial and academic workforce. The PI will continue to recruit women and minority graduate students into his research program for this project. Outreach to under-represented groups will include PI leadership and participation at CRA-W mentoring workshops for women and minority graduate students.The goal of the proposed research is to exploit deep learning to design new microarchitectural predictors capable of exploiting previously untapped levels of predictability in program behavior to improve performance, power, and energy. Deep neural networks will be used to greatly improve the accuracy of microarchitectural predictors. This project will first explore latency-tolerant cache locality predictors, then move to control-flow prediction that has tighter timing constraints. Proposed predictors will be evaluated in a variety of contexts representing modern workloads at scales from mobile phones to datacenters. The research incurs a high-risk because no deep neural network has even been developed to operate at the sub-nanosecond level. However, the research offers a high-payoff due to the tremendous potential to improve performance. Results will be manifested through students' theses and dissertations as well as publication in top-tier architecture venues.