CSR: Small: Memory-Centric Real-Time Scheduling for Multicore Embedded Systems

CSR：小型：多核嵌入式系统以内存为中心的实时调度

• 批准号: 1219064
• 负责人: Marco Caccamo
• 金额: $ 50万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-09-01 至 2016-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1219064&HistoricalAwards=false
• 关键词: CSR; Small; Memory; Centric; Real

In modern automotive and avionics applications, the use of multiple sensors and especially real-time imaging sensors creates unprecedented workloads. From a computational perspective, multicore architectures have become mainstream; however, as a multicore chip is expected to process increasing volumes of data in real-time, the memory hierarchy becomes the bottleneck resource. In the worst case, task execution times can grow linearly with the number of cores in the system. This research aims at laying foundations for a modern memory-centric real-time scheduling theory that can effectively co-schedule the use of the memory hierarchy, the cores, and the on-chip network, including the I/O channels. According to the vision of Memory-Centric Scheduling, when the memory hierarchy is the system bottleneck, memory accesses should be scheduled to achieve high memory utilization. Performance of a real-time multicore system should be measured in terms of schedulable memory utilization rather than just core utilization. Ideally, the real-time constraints should be met as long as total memory utilization of all real-time applications (across all the cores contending for shared memory) is below 100%.The potential economic and social benefits of this research are significant since the developed theory will greatly increase the temporal predictability of embedded multicore software systems in general, while in particular reducing cost and time required to achieve the necessary safety certification of next generation avionic multicore computing architectures. As the new scheduling theory is being developed, key elements will be incorporated into graduate classes in real-time computing and then migrated to senior undergraduate classes.

在现代汽车和航空电子应用中，使用多个传感器，特别是实时成像传感器，会产生前所未有的工作负载。从计算的角度来看，多核架构已经成为主流;然而，随着多核芯片被期望实时处理越来越多的数据量，存储器层次结构成为瓶颈资源。在最坏的情况下，任务执行时间可以随着系统中的内核数量线性增长。这项研究的目的是奠定基础的现代内存为中心的实时调度理论，可以有效地协同调度使用的存储器层次结构，核心和片上网络，包括I/O通道。根据以内存为中心的调度思想，当内存层次结构成为系统瓶颈时，应该对内存访问进行调度以实现高的内存利用率。实时多核系统的性能应该根据可扩展内存利用率来衡量，而不仅仅是核心利用率。理想情况下，只要所有实时应用程序的总内存利用率（在竞争共享内存的所有核之间）低于100%。这项研究的潜在经济和社会效益是显著的，因为所开发的理论将大大提高嵌入式多核软件系统的时间可预测性，同时特别地减少了实现下一代航空电子多核计算体系结构的必要安全认证所需的成本和时间。随着新的调度理论的发展，关键要素将被纳入研究生班的实时计算，然后迁移到高年级本科班。