CSR: Small: Cache-Coherent Accelerators for Efficient Persistent Memory Programming

CSR：小型：用于高效持久内存编程的缓存一致性加速器

• 批准号: 2245999
• 负责人: Ryan Stutsman
• 金额: $ 59.29万
• 依托单位: University of Utah
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2245999&HistoricalAwards=false
• 关键词: CSR; Small; Cache; Coherent; Accelerators

Persistent memory (PM) is a new class of computer storage that upends the model that computer systems have used for more than half a century. Unlike conventional storage devices, PM can be accessed by CPUs as if it were memory. Accessing storage this way can be implemented in hardware instead of software, so it can be accessed more quickly and efficiently than conventional storage devices. Even so, it persists across faults and power failures. This proposal seeks to convert existing software to use this faster PM-based storage without requiring programmers to change their code while providing safety during crashes and power failures. Unlike existing approaches, the proposed approach does this using emerging commercially available hardware; hence, it is fast and efficient since it does not reintroduce software to the CPU storage access path.The improved computer system memory performance, efficiency, and capacity that PM provides when combined with this project's accelerated crash consistency will have broad benefits to many private and public sector applications. Many of the costs that virtually all database systems introduce to survive crashes and power failures can be mitigated by the proposed approach. Furthermore, applications that process and modify massive data sets in real-time including data center applications, social networks, and machine learning training and inference over changing data sets can all benefit from improved scale, performance, and efficiency. Hence, this work can help accelerate code in the data center applications that are used by billions of users daily.This project will also carry out several outreach and educational activities along with specific collaborations to encourage industry adoption including a tutorial, a new graduate seminar, new modules for graduate and undergraduate courses, and a new course lab assignment. Additionally, the PI will host two incoming undergraduate students from an underrepresented group for research rotations as well as host two undergraduates through the NSF REU program. The resulting tools, framework, and accelerator code will be developed in the open under a permissive license to support use and development both in academia and industry, and it will be packaged for easy use and deployment on open platforms.In more detail, PM support in recent CPU architectures allows CPUs to access and manipulate massive data sets, lowering data access times from 10s of microseconds to 100s of nanoseconds. However, system crashes in the middle of modifying persistent data structures can lead to inconsistencies that are difficult or impossible to repair; thus, today PM-based data structures still place software on the path to storage access to provide extra steps for crash consistency. The key insight of this proposal is that the interposition needed on PM data accesses for crash consistency can be done fully in hardware without any changes to existing CPU architectures by using newly emerging cache-coherent accelerators and field-programmable gate arrays (FPGAs). Furthermore, it can be done with existing, off-the-shelf code for data structures that were designed without PM in mind. In the proposed approach, applications interact with PM through a hardware FPGA, which carefully controls how changes are propagated to PM to provide crash consistency. Since this interposition is in hardware it is efficient, which helps realize the full performance potential of PM's direct load/store interface. Also, this new approach works well with CPUs' cache coherence protocols, so CPUs can cache PM data more aggressively than is safe with direct PM access; in turn, this makes the proposed approach faster than direct load/store access to PM in many cases. Finally, the proposed work includes using this cache-coherent accelerator to provide replicated, fault-tolerant PM, and it includes new approaches to hiding PM and remote memory access times by implementing new, intelligent prefetching policies in hardware without CPU changes.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

持续记忆（PM）是一种新的计算机存储，它颠覆了计算机系统已使用了半个多世纪的模型。与传统的存储设备不同，CPU可以访问PM，就好像是内存一样。以这种方式访问​​存储可以在硬件而不是软件中实现，因此比传统存储设备可以更快，更有效地访问它。即便如此，它仍然存在于故障和权力故障。该建议旨在将现有软件转换为使用此更快的基于PM的存储，而无需程序员在撞车和电源故障期间提供安全性的同时更改代码。与现有方法不同，建议的方法使用新兴的市售硬件来做到这一点。因此，这是快速而有效的，因为它不会将软件重新引入CPU存储访问路径。在与该项目加速的崩溃一致性结合使用时，PM提供的改进的计算机系统内存性能，效率和容量将对许多私人和公共部门应用具有广泛的好处。所提出的方法几乎所有数据库系统都引入了许多数据库系统为生存崩溃和功率故障而引入的许多成本。此外，对实时处理和修改大量数据集的应用程序，包括数据中心应用程序，社交网络以及机器学习培训以及对不断变化的数据集的推断，都可以从提高的规模，性能和效率中受益。因此，这项工作可以帮助加速数十亿用户每天使用的数据中心应用程序中的代码。该项目还将开展几项宣传和教育活动以及具体的合作，以鼓励行业采用，包括教程，包括新的研究生研讨会，新的研究生和本科课程的新模块，以及新的课程实验室分配。此外，PI将主持来自一个人数不足的研究轮换小组的两名新本科生，并通过NSF REU计划主持两名本科生。所得的工具，框架和加速器代码将在公开的允许许可下开发，以支持学术界和行业的使用和开发，并将其包装以易于使用和在开放式平台上进行包装。在更详细的详细信息中，最近的CPU体系结构中的PM支持允许CPU允许CPU访问和操作大量数据集，从10ss of 10ss of 10ss consect of 10ssecs of 10ss of 10ss of 10ss of 10ssecects of 10ssecects of 10ss of 10ssecects inseconds of 10ssecsects inseconds inseconds inseconds inseconds of 100ssods inseconds inseconds insecects。但是，在修改持久数据结构的过程中，系统崩溃可能导致难以修复或不可能修复的不一致。因此，如今，基于PM的数据结构仍然将软件放在存储访问的路径上，以提供额外的碰撞一致性步骤。该提案的关键见解是，可以在硬件中完全完成PM数据访问中所需的插入，而无需使用新出现的Cache-Cache-Coherent加速器和现场可编程的GATE阵列（FPGAS），而无需对现有CPU架构进行任何更改。此外，可以使用无需牢记PM设计的数据结构的现有现成的代码来完成。在拟议的方法中，应用程序通过硬件FPGA与PM进行交互，该硬件仔细控制了如何将变化传播到PM以提供碰撞一致性。由于此插入是在硬件中，因此有效，这有助于实现PM直接负载/存储接口的全部性能潜力。此外，这种新方法与CPU的高速缓存相干协议很好地搭配，因此CPU可以比直接访问PM访问更为积极地缓存PM数据。反过来，在许多情况下，这使得提出的方法比直接加载/存储对PM的访问更快。 Finally, the proposed work includes using this cache-coherent accelerator to provide replicated, fault-tolerant PM, and it includes new approaches to hiding PM and remote memory access times by implementing new, intelligent prefetching policies in hardware without CPU changes.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.