CAREER: Predicting Timing Violations: A New Direction for Robust System Design

职业：预测时序违规：鲁棒系统设计的新方向

• 批准号: 1253024
• 负责人: Sanghamitra Roy
• 金额: $ 46.61万
• 依托单位: Utah State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-03-01 至 2021-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1253024&HistoricalAwards=false
• 关键词: CAREER; Predicting; Timing; Violations; New

Timing violations, an artifact of rapid technology scaling, embody a central reliability challenge in microprocessor design. A vast body of existing techniques in the landscape of timing violations fall under two broad categories: reactive and proactive. In both of these schemes, the lack of sufficient time in identifying an upcoming timing violation limits the scope of corrective techniques, incurring a large recovery overhead, or loss in fault coverage, respectively. Using a cross-layer analysis combining information from the application, architecture and circuit layers, this CAREER project demonstrates that timing violations can be predicted several clock cycles early. Early prediction of timing violations can offer a vast leverage in robust system design, opening up a promising direction for future systems research. In this paradigm, microprocessors can operate at a tighter frequency, where predictable errors frequently occur and are tolerated with minimal performance loss. Such a system design style can reshape physical design algorithms, boosting the energy efficient frontiers for microprocessor components. Research in the nascent area of cross-layer design will enable circuit designers and system architects to increase collaborative design, and develop affordable, energy efficient and reliable computer systems. The rapid growth and evolution of integrated circuits creates a huge demand of Computer Engineering skill sets for addressing upcoming challenges. The CAREER project seeks to create a stream of future engineers capable of tackling growing unreliability in integrated circuits through focused knowledge dissemination. Undergraduates, women and minorities will be actively sought for participation through the existing platforms at Utah State University such as the Society of Women Engineers (SWE), Engineering State and Center for Women and Gender (CWG) programs.

时序违规是快速技术扩展的产物，体现了微处理器设计中的核心可靠性挑战。大量的现有技术在时序违规的景观分为两大类：反应和主动。在这两种方案中，缺乏足够的时间来识别即将到来的时序违规限制了纠正技术的范围，分别导致了大的恢复开销或故障覆盖率的损失。使用跨层分析结合信息的应用程序，架构和电路层，这个CAREER项目表明，时序违规可以预测几个时钟周期提前。时序违规的早期预测可以在鲁棒系统设计中提供巨大的杠杆作用，为未来的系统研究开辟了一个有前途的方向。在这种模式下，微处理器可以在更严格的频率下运行，其中经常发生可预测的错误，并且可以容忍最小的性能损失。这样的系统设计风格可以重塑物理设计算法，提高微处理器组件的能效前沿。跨层设计这一新兴领域的研究将使电路设计师和系统架构师能够增加协作设计，并开发出价格合理、节能和可靠的计算机系统。集成电路的快速增长和发展为应对即将到来的挑战创造了对计算机工程技能的巨大需求。CAREER项目旨在通过集中的知识传播，创造一批能够解决集成电路日益增长的不可靠性的未来工程师。将通过犹他州州立大学现有的平台，如女工程师协会（SWE），工程州和妇女与性别中心（CWG）计划，积极寻求本科生，妇女和少数民族的参与。

项目成果

UPTPU: Improving Energy Efficiency of a Tensor Processing Unit through Underutilization Based Power-Gating

• DOI: 10.1109/dac18074.2021.9586224
• 发表时间: 2021-12
• 期刊: 2021 58th ACM/IEEE Design Automation Conference (DAC)
• 作者: Pramesh Pandey;N. D. Gundi;Koushik Chakraborty;Sanghamitra Roy