CAREER: Sustaining Moore's Law Through Introspective Computing: A Comprehensive System For Reliability and Energy Optimization in Modern Computing Devices

无论人们是关心数据中心的碳足迹还是移动设备的电池寿命，微处理器都是能源的主要消费者。晶体管技术的规模化，摩尔表示的是谁的速度？s定律是晶体管尺寸减小到纳米尺寸的规律。从历史上看，这种规模导致了性能和能源效率的显著提高，但最近的规模带来了严重的可靠性挑战，因为在近原子规模上构建组件很困难。为了确保正确性，芯片在静态和最坏情况下的安全裕度下运行，这些裕度占CPU总能耗的70%以上。该研究项目通过智能地收紧安全边际，并使其动态，以确保可靠的运行，大幅减少能源消耗，专门解决了能源浪费问题。这项研究的成功将大大减少半导体设备的能源浪费，从而提高电池寿命、环境影响和运营成本。它还将鼓励在一系列计算技术中使用持续的自我调整和适应。除了依赖于电源电压和器件温度外，晶体管的功率和开关延迟随着掺杂剂的随机波动和老化而发生很大的变化。在目前的实践中，影响晶体管功耗和延迟的因素的最坏情况组合用于确定器件的几何形状和定义工作电压保护带。这确保了可靠的运行，但会导致不必要的能源浪费，因为最坏的组合在现实中不太可能发生。在这项工作中，机器学习用于关联影响电路延迟和功率的环境和可控因素，并动态预测最小安全保护带。如果使用防错误组件，则可以完全消除保护带。为了实现最大的效益，系统设计在电路层、架构层和软件层之间进行了优化。结合机器学习、主动闭环控制和成本/效益驱动的执行器和片上传感器分配方法，电路设计师和架构师提供了一种全面的方法来创建内省计算设备，这些设备可以显着降低能耗，并自动适应所有环境和工作负载条件。

Whether one is concerned about data-center carbon footprint or battery life of mobile devices, the microprocessor is a dominating consumer of energy. Transistor technology scaling, whose rate is expressed by Moore?s Law, is a regular progression of transistor size reductions down to nanometer dimensions. Historically, this scaling has led to significant improvements in performance and energy efficiency, but more recently scaling has created severe reliability challenges due to difficulties in building components at near-atomic scale. To ensure correctness, chips are operated with static and worst-case safety margins that account for more than 70% of the total energy used by a CPU. This research program specifically addresses that energy wastage by intelligently tightening safety margins and making them dynamic in order to ensure reliable operation with dramatic reductions in expended energy. The success of this research effort will lead to substantial reduction in energy wasted by semiconductor devices for the purpose of improving battery life, environmental impact, and operating costs. It will also encourage the use of continuous self-adjustment and adaptation across an array of computing technologies.In addition to being dependent on the power supply voltage and device temperature, the power and switching delay of a transistor varies substantially with random dopant fluctuation and aging. In current practice, the worst-case combination of factors that affect transistor power consumption and delay are used to size device geometries and define an operating voltage guard band. This ensures reliable operation but leads to unnecessary energy wastage, as the worst-case combinations are unlikely to occur in reality. In this work, machine learning is used to correlate environmental and controllable factors that affect circuit delay and power and dynamically predict the minimum safe guard band. If error-resilient components are used, the guard band can be eliminated entirely. To realize maximum benefit, the system design is optimized across the boundaries of circuit, architectural, and software layers. Combining machine learning, proactive closed-loop control, and a cost/benefit-driven approach to actuator and on-chip sensor allocation, circuit designers and architects are provided with a comprehensive methodology for creating introspective computing devices that dramatically lower energy and adapt automatically to all environmental and workload conditions.