CAREER: Sustaining Moore's Law Through Introspective Computing: A Comprehensive System For Reliability and Energy Optimization in Modern Computing Devices

无论是关注数据中心的碳排放还是移动设备的电池寿命，微处理器都是主要的能源消耗者。晶体管技术的规模化是晶体管尺寸缩小到纳米尺度的规律性过程，其速度由摩尔-S定律表示。从历史上看，这种扩展带来了性能和能源效率的显著提高，但最近，由于难以构建近原子规模的组件，扩展带来了严重的可靠性挑战。为了确保正确性，芯片在静态和最坏情况下的安全裕度下运行，这些裕度占CPU总能耗的70%以上。这项研究计划通过智能地收紧安全裕度并使其具有动态化来专门解决能源浪费问题，以确保可靠的运行，同时大幅减少能源消耗。这项研究的成功将大大减少半导体器件所浪费的能量，以提高电池寿命、环境影响和运营成本。它还将鼓励在一系列计算技术中使用连续的自我调整和适应。除了依赖于电源电压和器件温度外，晶体管的功率和开关延迟随随机掺杂波动和老化而变化很大。在目前的实践中，影响晶体管功耗和延迟的因素的最坏情况组合被用来确定器件几何尺寸和定义工作电压保护带。这确保了可靠的运行，但导致了不必要的能量浪费，因为最坏的情况组合在现实中不太可能发生。在这项工作中，机器学习被用来关联影响电路延迟和功率的环境和可控因素，并动态地预测最小安全保护频带。如果使用容错组件，则可以完全消除保护频带。为了实现最大效益，系统设计跨越了电路、架构和软件层的界限进行了优化。结合机器学习、主动闭环控制以及成本/效益驱动的执行器和片上传感器分配方法，电路设计者和架构师可获得一套全面的方法来创建可大幅降低能耗并自动适应所有环境和工作负载条件的自省计算设备。

Whether one is concerned about data-center carbon footprint or battery life of mobile devices, the microprocessor is a dominating consumer of energy. Transistor technology scaling, whose rate is expressed by Moore?s Law, is a regular progression of transistor size reductions down to nanometer dimensions. Historically, this scaling has led to significant improvements in performance and energy efficiency, but more recently scaling has created severe reliability challenges due to difficulties in building components at near-atomic scale. To ensure correctness, chips are operated with static and worst-case safety margins that account for more than 70% of the total energy used by a CPU. This research program specifically addresses that energy wastage by intelligently tightening safety margins and making them dynamic in order to ensure reliable operation with dramatic reductions in expended energy. The success of this research effort will lead to substantial reduction in energy wasted by semiconductor devices for the purpose of improving battery life, environmental impact, and operating costs. It will also encourage the use of continuous self-adjustment and adaptation across an array of computing technologies.In addition to being dependent on the power supply voltage and device temperature, the power and switching delay of a transistor varies substantially with random dopant fluctuation and aging. In current practice, the worst-case combination of factors that affect transistor power consumption and delay are used to size device geometries and define an operating voltage guard band. This ensures reliable operation but leads to unnecessary energy wastage, as the worst-case combinations are unlikely to occur in reality. In this work, machine learning is used to correlate environmental and controllable factors that affect circuit delay and power and dynamically predict the minimum safe guard band. If error-resilient components are used, the guard band can be eliminated entirely. To realize maximum benefit, the system design is optimized across the boundaries of circuit, architectural, and software layers. Combining machine learning, proactive closed-loop control, and a cost/benefit-driven approach to actuator and on-chip sensor allocation, circuit designers and architects are provided with a comprehensive methodology for creating introspective computing devices that dramatically lower energy and adapt automatically to all environmental and workload conditions.