XPS: FULL: DSD: Collaborative Research: Moving the Abyss: Database Management on Future 1000-core Processors

XPS：完整：DSD：协作研究：移动深渊：未来 1000 核处理器上的数据库管理

• 批准号: 1438955
• 负责人: Andrew Pavlo
• 金额: $ 49.96万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-09-01 至 2018-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1438955&HistoricalAwards=false
• 关键词: XPS; FULL; DSD; Collaborative; Research

There are fundamental problems to speeding up CPUs beyond what ispossible today. Because individual transistors are not getting anyfaster, manufacturers like Intel and AMD are no longer able to getmassive performance improvements just by increasing clock speeds(e.g., going from 2GHz to 10GHz). To overcome this, future CPUs willcontain hundreds to thousands of smaller computational cores on asingle chip which will all run at the speed similar to currentprocessors (e.g., 2GHz). This means that each single core will only beas powerful as current CPUs, but that the total aggregate power of allthe cores will be significantly more than what is possible today. Animportant problem with the advent of these new CPUs is that thedatabase systems that are used in all aspects of our society areill-suited for this change. Such database systems are used to storeand access data for a variety of applications, including on-linebusiness (e.g., Google, Facebook), scientific instruments (e.g.,astronomical telescopes), and medicine (e.g., MRI scanners). Thereason that they are not ready to handle these new "many-core CPUs" isbecause most of them use ideas that were designed in the 1970s and1980s when processors only had a single core. Thus, the purpose ofthis project is to develop both software and hardware technologiesthat will allow database systems to utilize the full computationalpower of future CPU architectures. The results of this project willenable organizations to deploy future applications on fewer machinesthat use less energy than what is currently used today.Computer architectures are moving towards an era dominated bymany-core machines with hundreds of cores on a single chip. Thisunprecedented level of on-chip parallelism introduces a new dimensionto scalability that current database management systems (DBMSs) werenot designed for. In particular, it becomes exceedingly difficult forthe DBMS to perform concurrency control, logging, and indexingefficiently. With hundreds of threads running in parallel, thecomplexity of coordinating competing reads and writes to datadiminishes the benefits of increased core counts. Thus, in thisproject we propose to develop a software-hardware co-design approachfor DBMSs in the many-core era. On the software side, rather thanattempting to remove scalability bottlenecks of existing DBMSarchitectures through incremental improvements, the PIs seek a bottom-upapproach where the architecture is designed to target many-coresystems from inception. On the hardware side, instead of simply addingmore cores to a single chip, the PIs will design new hardware componentsthat can unburden the software system from computationally criticaltasks.For further information see project web site at:http://db.cs.cmu.edu/projects/1000cores/

将CPU加速到今天的可能性之外，这是有根本的问题。由于单个晶体管没有得到任何速度，因此像Intel和AMD这样的制造商不再能够仅通过提高时钟速度（例如，从2GHz到10GHz）来提高性能。为了克服这一点，未来的CPU将在Asingle芯片上数百至成千上万的较小的计算核心，这些计算芯都将以类似于CurrentProcessors（例如2GHz）的速度运行。这意味着每个核心只能像当前的CPU一样强大，但是所有核心的总骨料能力将大大超过当今的可能性。这些新CPU的出现的动画问题是，在我们社会各个方面使用的THEDATABASE系统都适合这种变化。此类数据库系统用于用于访问各种应用程序的访问数据，包括on-lineBusiness（例如Google，Facebook），Scientific Instruments（例如，天文望远镜）和医学（例如MRI扫描仪）。季节，他们还没有准备好处理这些新的“多核CPU”，因为它们中的大多数都使用了1970年代和1980年代设计的想法，而处理器只有一个核心。因此，此项目的目的是开发软件和硬件TechnologiestHat将允许数据库系统利用未来CPU架构的完整计算能力。该项目的结果将在更少的Machinesthat上部署未来的应用程序的结果比当前使用的功能要少。.computer架构正朝着以单个芯片上数百个核心为主导的bymany-Core机器主导的ERA。片上并行性的这种非级别级别引入了当前数据库管理系统（DBMSS）WERENOT设计的新尺寸可伸缩性。特别是，DBMS无法对并发控制，记录和索引有效地进行极其困难。随着数百个线程并联，协调竞争的读取和写作以datadiminish的核心读取可以增加核心计数的好处。因此，在此项目中，我们建议在多核时代为DBMS开发软件硬件共同设计方法。在软件方面，PIS在软件方面，而不是通过逐步改进来删除现有DBMSarchitectures的可扩展性瓶颈，而是寻求自下而上的接口，其中该体系结构旨在针对启动的多个核心系统。在硬件方面，PIS将设计新的硬件组件，而不是简单地将核心添加到单个芯片中，可以从Computationally BricyTask中解开软件系统的负担。有关更多信息，请参见项目网站：http：//db.cmu.edu.edu/projects/1000Cores/