EAGER: Locality-Aware Data Access Control for Future 1000-core Processors

EAGER：面向未来 1000 核处理器的位置感知数据访问控制

• 批准号: 1452327
• 负责人: Omer Khan
• 金额: $ 10万
• 依托单位: University of Connecticut
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-08-01 至 2017-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1452327&HistoricalAwards=false
• 关键词: EAGER; Locality; Aware; Data; Access

Computer architectures will soon approach an era of single-chip multicore processors with hundreds or even thousands of heterogeneous cores connected via complex interconnection networks and cache hierarchies. These many-core processors will concurrently execute next generation applications, such as big data analytics, to exploit parallelism and specialization for power-performance efficiency. Furthermore, new memory technologies will be integrated to minimize energy-inefficient off-chip accesses. However, the technology trends indicate that wire scaling will slow down dramatically as compared to computation. The cost of moving data efficiently through the future many-core processors will become a major challenge. The increasing core counts with heterogeneous computation and communication capabilities, as well as applications that process massive data with varying degrees of locality and reuse, will introduce data access variations at different layers of the processor. This project proposes to dynamically exploit and co-optimize this variability in locality and reuse of data as it flows through the processor resources. The strategy is to adopt a hardware-software co-design approach, and develop fine-through-coarse-grain cross-layer mechanisms for locality-optimal data access in future many-core processors. This will be achieved using a novel locality-aware data access control utility (LDAC) that intelligently and cooperatively orchestrates data movement in the shared heterogeneous processor resources to deliver the efficiency promise. If successful, this project will be a major step forward towards a new computational model where runtime management of processor efficiency can be utilized to make tradeoffs with security, privacy, resilience, or accuracy of computation. The PI will build a holistic prototype simulation environment to demonstrate the efficacy of the proposed locality-optimal data access utility. The development of simulator infrastructure and a many-core prototype will allow the products of this research to be disseminated widely. This project will introduce practical multicore computing to graduate and undergraduate students with a focus on writing parallel software for performance and energy efficiency. The research outcomes will enable the design of future many-core processors that use low energy to execute parallel applications efficiently.

计算机体系结构将很快进入单芯片多核处理器时代，这些处理器具有通过复杂的互连网络和高速缓存层次结构连接的数百甚至数千个异构核心。这些众核处理器将同时执行下一代应用程序，例如大数据分析，以利用并行性和专业化来提高功率性能效率。此外，还将集成新的存储器技术，以最大限度地减少能源效率低下的片外访问。然而，技术趋势表明，与计算相比，线缩放将显着减慢。通过未来的众核处理器有效地移动数据的成本将成为一个重大挑战。随着计算和通信能力的不断增加，以及处理大量数据的应用程序具有不同程度的本地性和重用性，将在处理器的不同层引入数据访问变化。这个项目建议动态地利用和协同优化本地的这种可变性，并在数据流经处理器资源时重用数据。该策略是采用软硬件协同设计的方法，并开发从细到粗的跨层机制，用于未来众核处理器中的局部最优数据访问。这将通过使用一种新颖的本地感知数据访问控制实用程序（LDAC）来实现，该实用程序智能地和协作地编排共享异构处理器资源中的数据移动，以实现效率承诺。如果成功，该项目将是迈向新计算模型的重要一步，在新计算模型中，可以利用处理器效率的运行时管理来权衡安全性、隐私性、弹性或计算准确性。PI将建立一个整体的原型仿真环境，以证明所提出的局部优化数据访问实用程序的有效性。模拟器基础设施和多核原型的开发将使这项研究的产品得到广泛传播。这个项目将向研究生和本科生介绍实用的多核计算，重点是编写性能和能源效率的并行软件。研究成果将使未来的众核处理器的设计，使用低能耗，高效地执行并行应用程序。