CAREER: A Hardware and Software Architecture for Data-Centric Parallel Computing

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Energy efficiency is the key challenge facing computer systems. To improveperformance under a limited energy budget, systems are becoming increasinglyparallel, featuring many smaller and simpler cores, and heterogeneous,featuring cores specialized for certain tasks. Even with these improvements,two critical challenges remain. First, without reducing data movement, memoryaccesses and communication will dominate energy consumption. Thus, limitingdata movement must become a primary design objective. Second, these systemswill be highly complex, and will need powerful abstractions to shieldprogrammers from this complexity. Current systems are designed in acomputation-centric way that is a poor match for these challenges. Memoryhierarchies are hardware-managed and opaque to software, which needlesslyincreases data movement; and runtimes lack the proper hardware mechanisms andsoftware policies to manage heterogeneous resources efficiently.This research project takes a holistic approach to addressing these challenges, byco-designing an architecture and runtime system that efficiently run dynamicparallel applications on systems with heterogeneous cores and memories.Redesigning hardware to be directly exploited by a dynamic runtime enables (a)many more opportunities to reduce data movement, (b) better usage ofheterogeneous resources, and (c) much faster adaptation to changing applicationneeds and available resources. Three key components underlie this design.First, a scalable memory system incorporates combinations of heterogeneousmemory technologies to improve efficiency, and exposes them to software, whichcan divide these physical memories into many virtual cache and memoryhierarchies to finely control data placement. Second, specialized programmableengines orchestrate communication among cores, accelerate intensive runtimefunctions such as load balancing, and monitor how tasks use hardware resourcesto guide runtime decisions. Third, a hardware-accelerated runtime leveragesthis novel architectural support to place data and computation to minimize datamovement, use the most suitable core for each task, and quickly respond tochanging application needs. This runtime targets a high-level programming modelthat lets programmers express fine-grained and irregular task, data, andpipeline parallelism. These techniques build on an analytical design approachthat makes hardware easy to understand and predict, and enables runtimes tonavigate multi-dimensional tradeoffs efficiently.If successful, this project will make heterogeneous systems more efficient,more broadly applicable, and easier to program. It will especially benefitapplications with dynamic and fine-grained parallelism, advancing key emergingdomains where these workloads are pervasive, such as graph analytics and onlinedata-intensive services. In addition, the infrastructure developed as part ofthis project will be publicly released, enabling others to build on the resultsof this work.