CAREER: A Hardware and Software Architecture for Data-Centric Parallel Computing

能源效率是计算机系统面临的关键挑战。为了在有限的能源预算下提高性能，系统正变得越来越并行，具有许多更小和更简单的核心，并且具有异构性，具有专门用于某些任务的核心。即使有了这些改进，仍然存在两个关键挑战。首先，在不减少数据移动的情况下，内存访问和通信将主导能源消耗。因此，限制数据移动必须成为主要的设计目标。其次，这些系统将非常复杂，需要强大的抽象来保护程序员免受这种复杂性的影响。目前的系统是以计算为中心的设计方式，不能很好地满足这些挑战。内存层次结构由硬件管理且对软件不透明，这不必要地增加数据移动；并且运行时缺乏适当的硬件机制和软件策略来有效地管理异类资源。本研究项目采用整体方法来解决这些挑战，通过共同设计一个架构和运行时系统来高效地在具有异质内核和内存的系统上运行动态并行应用程序。重新设计将被动态运行时直接利用的硬件使得(A)有更多机会减少数据移动，(B)更好地利用异类资源，以及(C)更快地适应不断变化的应用程序需求和可用资源。首先，一个可扩展的存储系统结合了各种不同的存储技术来提高效率，并将它们暴露给软件，软件可以将这些物理内存划分为许多虚拟缓存和存储层次，以精细地控制数据放置。其次，专门的可编程引擎协调核心之间的通信，加速负载平衡等密集运行时功能，并监控任务如何使用硬件资源来指导运行时决策。第三，硬件加速的运行时利用这种新颖的架构支持来放置数据和计算，以最大限度地减少数据移动，为每个任务使用最合适的内核，并快速响应不断变化的应用程序需求。此运行时以高级编程模型为目标，该模型允许程序员表达细粒度和不规则的任务、数据和流水线并行。这些技术建立在分析设计方法的基础上，使硬件易于理解和预测，并使运行时能够高效地进行多维权衡。如果成功，该项目将使不同的系统更高效、更广泛地适用和更容易编程。它将特别有利于具有动态和细粒度并行的应用程序，推进这些工作负载普遍存在的关键新兴领域，例如图形分析和在线数据密集型服务。此外，作为该项目的一部分开发的基础设施将被公开发布，使其他人能够在这项工作的结果的基础上继续发展。

Energy efficiency is the key challenge facing computer systems. To improveperformance under a limited energy budget, systems are becoming increasinglyparallel, featuring many smaller and simpler cores, and heterogeneous,featuring cores specialized for certain tasks. Even with these improvements,two critical challenges remain. First, without reducing data movement, memoryaccesses and communication will dominate energy consumption. Thus, limitingdata movement must become a primary design objective. Second, these systemswill be highly complex, and will need powerful abstractions to shieldprogrammers from this complexity. Current systems are designed in acomputation-centric way that is a poor match for these challenges. Memoryhierarchies are hardware-managed and opaque to software, which needlesslyincreases data movement; and runtimes lack the proper hardware mechanisms andsoftware policies to manage heterogeneous resources efficiently.This research project takes a holistic approach to addressing these challenges, byco-designing an architecture and runtime system that efficiently run dynamicparallel applications on systems with heterogeneous cores and memories.Redesigning hardware to be directly exploited by a dynamic runtime enables (a)many more opportunities to reduce data movement, (b) better usage ofheterogeneous resources, and (c) much faster adaptation to changing applicationneeds and available resources. Three key components underlie this design.First, a scalable memory system incorporates combinations of heterogeneousmemory technologies to improve efficiency, and exposes them to software, whichcan divide these physical memories into many virtual cache and memoryhierarchies to finely control data placement. Second, specialized programmableengines orchestrate communication among cores, accelerate intensive runtimefunctions such as load balancing, and monitor how tasks use hardware resourcesto guide runtime decisions. Third, a hardware-accelerated runtime leveragesthis novel architectural support to place data and computation to minimize datamovement, use the most suitable core for each task, and quickly respond tochanging application needs. This runtime targets a high-level programming modelthat lets programmers express fine-grained and irregular task, data, andpipeline parallelism. These techniques build on an analytical design approachthat makes hardware easy to understand and predict, and enables runtimes tonavigate multi-dimensional tradeoffs efficiently.If successful, this project will make heterogeneous systems more efficient,more broadly applicable, and easier to program. It will especially benefitapplications with dynamic and fine-grained parallelism, advancing key emergingdomains where these workloads are pervasive, such as graph analytics and onlinedata-intensive services. In addition, the infrastructure developed as part ofthis project will be publicly released, enabling others to build on the resultsof this work.