CAREER: A Hardware and Software Architecture for Data-Centric Parallel Computing

职业：以数据为中心的并行计算的硬件和软件架构

• 批准号: 1452994
• 负责人: Daniel Sanchez Martin
• 金额: $ 50万
• 依托单位: Massachusetts Institute of Technology
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-02-15 至 2020-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1452994&HistoricalAwards=false
• 关键词: CAREER; Hardware; Software; Architecture; Data

Energy efficiency is the key challenge facing computer systems. To improveperformance under a limited energy budget, systems are becoming increasinglyparallel, featuring many smaller and simpler cores, and heterogeneous,featuring cores specialized for certain tasks. Even with these improvements,two critical challenges remain. First, without reducing data movement, memoryaccesses and communication will dominate energy consumption. Thus, limitingdata movement must become a primary design objective. Second, these systemswill be highly complex, and will need powerful abstractions to shieldprogrammers from this complexity. Current systems are designed in acomputation-centric way that is a poor match for these challenges. Memoryhierarchies are hardware-managed and opaque to software, which needlesslyincreases data movement; and runtimes lack the proper hardware mechanisms andsoftware policies to manage heterogeneous resources efficiently.This research project takes a holistic approach to addressing these challenges, byco-designing an architecture and runtime system that efficiently run dynamicparallel applications on systems with heterogeneous cores and memories.Redesigning hardware to be directly exploited by a dynamic runtime enables (a)many more opportunities to reduce data movement, (b) better usage ofheterogeneous resources, and (c) much faster adaptation to changing applicationneeds and available resources. Three key components underlie this design.First, a scalable memory system incorporates combinations of heterogeneousmemory technologies to improve efficiency, and exposes them to software, whichcan divide these physical memories into many virtual cache and memoryhierarchies to finely control data placement. Second, specialized programmableengines orchestrate communication among cores, accelerate intensive runtimefunctions such as load balancing, and monitor how tasks use hardware resourcesto guide runtime decisions. Third, a hardware-accelerated runtime leveragesthis novel architectural support to place data and computation to minimize datamovement, use the most suitable core for each task, and quickly respond tochanging application needs. This runtime targets a high-level programming modelthat lets programmers express fine-grained and irregular task, data, andpipeline parallelism. These techniques build on an analytical design approachthat makes hardware easy to understand and predict, and enables runtimes tonavigate multi-dimensional tradeoffs efficiently.If successful, this project will make heterogeneous systems more efficient,more broadly applicable, and easier to program. It will especially benefitapplications with dynamic and fine-grained parallelism, advancing key emergingdomains where these workloads are pervasive, such as graph analytics and onlinedata-intensive services. In addition, the infrastructure developed as part ofthis project will be publicly released, enabling others to build on the resultsof this work.

能源效率是计算机系统面临的主要挑战。为了在有限的能源预算下提高性能，系统正在变得越来越并行，具有许多更小和更简单的核心，以及异构，具有专门用于某些任务的核心。即使有了这些改进，仍然存在两个关键挑战。首先，在不减少数据移动的情况下，内存访问和通信将主导能源消耗。因此，限制数据移动必须成为主要的设计目标。其次，这些系统将是高度复杂的，需要强大的抽象来保护程序员免受这种复杂性的影响。当前的系统是以计算为中心的方式设计的，这与这些挑战不匹配。存储器层次结构是硬件管理的，对软件不透明，这不必要地增加了数据移动;以及运行时缺乏适当的硬件机制和软件策略来有效地管理异构资源。本研究项目采取了一种整体的方法来解决这些挑战，副，副设计一个架构和运行时系统，在具有异构内核和内存的系统上有效地运行动态并行应用程序。动态运行时使得能够（a）有更多的机会来减少数据移动，（B）更好地使用异构资源，以及（c）更快地适应变化的应用需求和可用资源。这种设计有三个关键组成部分：首先，一个可扩展的内存系统结合了异构内存技术来提高效率，并将它们暴露给软件，软件可以将这些物理内存划分为许多虚拟缓存和内存层次结构，以精细地控制数据放置。第二，专门的可编程引擎协调核心之间的通信，加速负载平衡等密集型运行时功能，并监控任务如何使用硬件资源来指导运行时决策。第三，硬件加速的运行时将这种新颖的架构支持用于放置数据和计算，以最大限度地减少数据移动，为每个任务使用最合适的核心，并快速响应不断变化的应用程序需求。这个运行时的目标是一个高级编程模型，让程序员表达细粒度和不规则的任务，数据和管道并行。这些技术建立在分析设计方法之上，使硬件易于理解和预测，并使运行时能够有效地进行多维权衡。如果成功，该项目将使异构系统更有效，更广泛地适用，更容易编程。它将特别有利于具有动态和细粒度并行性的应用程序，推进这些工作负载普遍存在的关键新兴领域，例如图形分析和在线数据密集型服务。此外，作为该项目一部分开发的基础设施将公开发布，使其他人能够在此工作成果的基础上再接再厉。

项目成果

PHI: Architectural Support for Synchronization- and Bandwidth-Efficient Commutative Scatter Updates

• DOI: 10.1145/3352460.3358254
• 发表时间: 2019-10
• 期刊: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
• 作者: Anurag Mukkara;Nathan Beckmann;Daniel Sánchez

Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism

• DOI: 10.1109/micro.2018.00026
• 发表时间: 2018-10
• 期刊: 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
• 作者: M. C. Jeffrey;Victor A. Ying;Suvinay Subramanian;Hyun Ryong Lee;J. Emer;Daniel Sánchez

Chronos: Efficient Speculative Parallelism for Accelerators

• DOI: 10.1145/3373376.3378454
• 发表时间: 2020-03
• 期刊: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems
• 作者: Maleen Abeydeera;Daniel Sánchez

Livia: Data-Centric Computing Throughout the Memory Hierarchy

• DOI: 10.1145/3373376.3378497
• 发表时间: 2020-03
• 期刊: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems
• 作者: Elliot Lockerman;Axel Feldmann;Mohammad Bakhshalipour;Alexandru Stanescu;Shashwat Gupta;Daniel Sánchez;Nathan Beckmann

Safecracker: Leaking Secrets through Compressed Caches

Safecracker：通过压缩缓存泄露秘密

• DOI: 10.1145/3373376.3378453
• 发表时间: 2020
• 期刊: Proceedings of the 25th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-25
• 作者: Tsai, Po-An;Sanchez, Andres;Fletcher, Christopher W.;Sanchez, Daniel
• 通讯作者: Sanchez, Daniel