SHF: Small: A Scalable Architecture for Ubiquitous Parallelism

随着摩尔定律预测的性价比增长放缓，未来的计算机系统将需要利用越来越多的并行度来提高性能。实现这一目标需要新的技术来使大规模并行成为现实，因为当前的多核系统没有达到这一目标：它们浪费了应用程序中可用的大部分并行，并且编程极其困难。为了应对这些挑战，该项目正在研究一种新型的并行体系结构，该体系结构可以有效地扩展到数千个内核，并且几乎和顺序系统一样易于编程。它通过利用有序并行来实现这些好处，有序并行是通用的和丰富的，但在当前的系统中很难挖掘。正在研究的技术将使未来的并行系统更具通用性、可伸缩性和更易于编程。这些技术将特别有益于难以并行化的不规则应用程序，这些应用程序是新兴领域的关键，例如图形分析、机器学习和内存数据库。原型开发工作将为现有系统带来有序并行的好处。为了在保持顺序系统编程简单性的同时有效地并行绝大多数应用程序，该项目正在研究和开发以下技术：(1)分布式数据中心执行，它将细粒度有序并行和推测性执行扩展到具有数万核的机架规模的系统；(2)支持推测和非推测任务的无缝组合的表达执行模型，以提高效率和并行性；(3)自适应推测和资源管理技术，避免性能病态，减少浪费的工作，并更有效地利用这种新的体系结构；以及(4)该体系结构的基于FPGA的原型，它利用这些技术来利用有序并行和加速重要的应用。在这种体系结构中，程序由具有顺序约束的微小任务组成。该系统以推测和无序的方式执行任务，并有效地提前推测数千个任务，以发现有序并行。任务分布在接近其数据的位置运行，从而减少了数据移动，并允许系统跨多个芯片和主板进行扩展。早期的256核设计在通常被认为是顺序的程序上展示了近线性的可扩展性，比最先进的算法高出一到两个数量级。这一奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

With cost-performance gains predicted by Moore's Law slowing down, future computer systems will need to harness increasing amounts of parallelism to improve performance. Achieving this goal requires new techniques to make massive parallelism practical, as current multicore systems fall short of this goal: they squander most of the parallelism available in applications and are exceedingly hard to program. To address these challenges, this project is investigating a novel parallel architecture that efficiently scales to thousands of cores and is almost as easy to program as sequential systems. It achieves these benefits by exploiting ordered parallelism, which is general and abundant but is hard to mine in current systems. The technologies being investigated will make future parallel systems more versatile, scalable, and easier to program. These techniques will especially benefit hard-to-parallelize irregular applications that are key in emerging domains, such as graph analytics, machine learning, and in-memory databases. The prototyping efforts will bring the benefits of ordered parallelism to existing systems. Finally, the infrastructure developed as part of this project will be released publicly, enabling others to build on the results of this work.Towards the goal of efficiently parallelizing the vast majority of applications while retaining the programming simplicity of sequential systems, this project is investigating and developing the following techniques: (1) distributed data-centric execution, which scales fine-grained ordered parallelism and speculative execution to rack-scale systems with tens of thousands of cores; (2) an expressive execution model that supports seamless combinations of speculative and non-speculative tasks, improving efficiency and parallelism; (3) adaptive speculation and resource management techniques that avoid performance pathologies, reduce wasted work, and make more efficient use of this novel architecture; and (4) an FPGA-based prototype of this architecture that leverages these techniques to exploit ordered parallelism and accelerate important applications. In this architecture, programs consist of tiny tasks with order constraints. The system executes tasks speculatively and out of order, and efficiently speculates thousands of tasks ahead to uncover ordered parallelism. Tasks are distributed to run close to their data, reducing data movement and allowing the system to scale across multiple chips and boards. An early 256-core design demonstrates near-linear scalability on programs that are often deemed sequential, outperforming state-of-the-art algorithms by one to two orders of magnitude.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.