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CAREER: Addressing Deepening Variability Challenges for Next-Generation Margin-Free VLSI Computing Platform Design

CAREER: Addressing Deepening Variability Challenges for Next-Generation Margin-Free VLSI Computing Platform Design
职业生涯:解决下一代无裕度 VLSI 计算平台设计日益深化的可变性挑战
批准号:
1453142
负责人:
Mingoo Seok
金额:
$46.1万
依托单位:
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2015
资助国家:
美国
项目状态:
已结题
起止时间:
2015-03-01 至 2021-02-28

项目摘要

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中文摘要
翻译
这个CAREER项目的目标是解决当今计算芯片设计中不断加深的可变性挑战。在过去的四十年里,半导体技术取得了快速发展,使计算芯片成为我们信息时代的主要主力。目前正在继续努力进一步改进,但科学家和工程师最近观察到研究工作的回报越来越少。其主要原因之一是芯片内、芯片与芯片之间以及芯片寿命内的电路性能的不断增长的可变性。虽然传统的设计实践已经忽略了性能改进的可变性方面,但这方面现在已经变得过于引人注目,并且简单地丢弃它是不允许的。该项目还将在现有的框架内,针对初高中、大学生、研究生以及在职专业人士开展教育/推广计划。具体而言,该项目将通过创建跨设计层的整体技术,寻求收获计算芯片改进的可变部分的方法。重点是解决早期努力的关键局限性,例如,大的开销、有限的电压可伸缩性、隐藏的最坏情况设计实践以及新的变化源,使得芯片可以监控变化并动态地适应它们。特别是,该项目将追求低开销,电压可扩展的错误检测和校正方案,采用10- 100倍小传感器结构的细粒度片上热监控,以及现场自测试以适应芯片老化效应。研究结果将对各种计算系统产生影响--高性能、云、移动的、嵌入式和无处不在--所有这些系统都受到可变性的严重限制。
英文摘要
The goal of this CAREER project is to address deepening variability challenges in today's computing chip design. Over the last four decades, semiconductor technology has enjoyed rapid advancement, making computing chips the major workhorse for our information age. Continued efforts are ongoing for further improvements, and yet scientists and engineers have recently observed a diminishing return on the research efforts. One of the main causes for this is the ever-growing variability in circuit performance within a chip, from chip to chip, and over the lifetime of the chip. While conventional design practices have ignored the variability aspect for performance improvement, this aspect has now become too compelling and it is prohibitive to simply discard it. The project will essentially address this issue. The project also entails education/outreach plans targeting middle/high-school, undergraduate, and graduate students as well as working professionals within the current framework.More specifically, the project will seek a way to reap the variable portion of improvement in computing chips by creating holistic techniques across design layers. The focus is to address the critical limitations of earlier efforts, e.g., large overhead, limited voltage-scalability, hidden worst-case design practices, and new variation sources, so that chips can monitor variations and dynamically adapt to them. Particularly, the project will pursue low-overhead, voltage-scalable error-detection and correction schemes, fine-grained on-chip thermal monitoring with 10-100X smaller sensor fabrics, and in-field self-testing for adapting to chip-aging effects. The results of the research will have an impact across the spectrum of computing systems - high-performance, cloud, mobile, embedded, and ubiquitous - all of which are severely constrained by variability.
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