CAREER: Addressing Deepening Variability Challenges for Next-Generation Margin-Free VLSI Computing Platform Design

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The goal of this CAREER project is to address deepening variability challenges in today's computing chip design. Over the last four decades, semiconductor technology has enjoyed rapid advancement, making computing chips the major workhorse for our information age. Continued efforts are ongoing for further improvements, and yet scientists and engineers have recently observed a diminishing return on the research efforts. One of the main causes for this is the ever-growing variability in circuit performance within a chip, from chip to chip, and over the lifetime of the chip. While conventional design practices have ignored the variability aspect for performance improvement, this aspect has now become too compelling and it is prohibitive to simply discard it. The project will essentially address this issue. The project also entails education/outreach plans targeting middle/high-school, undergraduate, and graduate students as well as working professionals within the current framework.More specifically, the project will seek a way to reap the variable portion of improvement in computing chips by creating holistic techniques across design layers. The focus is to address the critical limitations of earlier efforts, e.g., large overhead, limited voltage-scalability, hidden worst-case design practices, and new variation sources, so that chips can monitor variations and dynamically adapt to them. Particularly, the project will pursue low-overhead, voltage-scalable error-detection and correction schemes, fine-grained on-chip thermal monitoring with 10-100X smaller sensor fabrics, and in-field self-testing for adapting to chip-aging effects. The results of the research will have an impact across the spectrum of computing systems - high-performance, cloud, mobile, embedded, and ubiquitous - all of which are severely constrained by variability.