CAREER: Synthesizing Highly Efficient Hardware Accelerators for Irregular Programs: A Synergistic Approach

这个CAREER研究项目旨在显著提高异构计算机体系结构的设计效率和质量，这些体系结构广泛集成了专门的硬件加速器，以继续为我们社会的各个方面提供必要的计算改进。实现这一目标需要开发一种新型的真正集成的设计自动化方法和工具，以便从高级程序中实现生产性建模、探索和硬件加速器的生成，特别是对于在新兴应用领域（如计算机视觉、机器学习、物理模拟和社会网络分析）中常见的不规则程序。该项目还有一个广泛而主题集中的教育推广计划，旨在培养下一代工程师和科学家，他们可以弥合软件和硬件设计范式之间的鸿沟。PI将为少数族裔高中学生提供动手设计课程，并为一年级本科生组织带有引人入胜的演示的工程研讨会，以提高他们对计算机工程的兴趣和参与。此外，PI将积极将研究成果整合到本科和研究生课程开发中，并利用产业合作有效地将异构计算的研究成果传播给更广泛的受众。技术扩展带来的好处越来越少，这导致人们对异构加速器丰富的系统架构越来越感兴趣，以提高在严格的功率和能源效率限制下的性能。不规则程序在许多重要的应用领域日益突出；但是这些程序很难在传统的数据并行加速器（如gpu）上并行化，因为它们通常表现出较不结构化的数据访问模式和难以预测的动态并行性。该项目旨在开发一个协同设计自动化框架，其中一组新颖的编程抽象、架构模板、综合优化算法和硬件原型都发挥协同作用，以克服不规则程序带来的许多挑战。具体来说，关键思想是自动生成软合成加速器，这些加速器能够将数据访问与计算分离，以容忍内存延迟，并执行运行时优化，以利用不规则的并行性。

This CAREER research project aims to significantly improve the design productivity and quality of heterogeneous computer architectures, which extensively integrate specialized hardware accelerators to continue to provide the computing improvements essential to all aspects of our society. Achieving this goal requires the development of a new class of truly integrated design automation methodologies and tools to enable productive modeling, exploration, and generation of hardware accelerators from high-level programs, especially for the irregular programs that are commonplace in emerging application domains such as computer vision, machine learning, physical simulation, and social network analytics. The project also has a broad yet thematically focused plan for educational outreach, which aims to cultivate the next generation of engineers and scientists who can bridge the chasm between the software and hardware design paradigms. The PI will lead hands-on design sessions for underrepresented minority high school students and organize engineering seminars with engaging demonstrations for first-year undergraduates to increase their interest and participation in computer engineering. In addition, the PI will actively integrate the research outcomes into undergraduate and graduate curriculum development, and leverage industrial collaborations to effectively disseminate the research results on heterogeneous computing to a broader audience.Diminished benefits of technology scaling have led to a growing interest in heterogeneous accelerator-rich system architectures to improve performance under tight power and energy efficiency constraints. Irregular programs are gaining prominence in many important application domains; but these programs are much more difficult to parallelize on conventional data-parallel accelerators such as GPUs, as they typically exhibit less-structured data access patterns and difficult-to-predict dynamic parallelism. This project aims to develop a synergistic design automation framework where a set of novel programming abstractions, architectural templates, synthesis optimization algorithms, and hardware prototypes all play concerted roles to overcome the many challenges raised by the irregular programs. Specifically, the key idea is to automatically generate softly synthesized accelerators that are capable of decoupling data access from computation for tolerating memory latency and performing run-time optimizations for exploiting the irregular parallelism.