CAREER: Synthesizing Highly Efficient Hardware Accelerators for Irregular Programs: A Synergistic Approach

职业：为不规则程序合成高效硬件加速器：一种协同方法

• 批准号: 1453378
• 负责人: Zhiru Zhang
• 金额: $ 45.3万
• 依托单位: Cornell University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-03-01 至 2022-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1453378&HistoricalAwards=false
• 关键词: CAREER; Synthesizing; Highly; Efficient; Hardware

This CAREER research project aims to significantly improve the design productivity and quality of heterogeneous computer architectures, which extensively integrate specialized hardware accelerators to continue to provide the computing improvements essential to all aspects of our society. Achieving this goal requires the development of a new class of truly integrated design automation methodologies and tools to enable productive modeling, exploration, and generation of hardware accelerators from high-level programs, especially for the irregular programs that are commonplace in emerging application domains such as computer vision, machine learning, physical simulation, and social network analytics. The project also has a broad yet thematically focused plan for educational outreach, which aims to cultivate the next generation of engineers and scientists who can bridge the chasm between the software and hardware design paradigms. The PI will lead hands-on design sessions for underrepresented minority high school students and organize engineering seminars with engaging demonstrations for first-year undergraduates to increase their interest and participation in computer engineering. In addition, the PI will actively integrate the research outcomes into undergraduate and graduate curriculum development, and leverage industrial collaborations to effectively disseminate the research results on heterogeneous computing to a broader audience.Diminished benefits of technology scaling have led to a growing interest in heterogeneous accelerator-rich system architectures to improve performance under tight power and energy efficiency constraints. Irregular programs are gaining prominence in many important application domains; but these programs are much more difficult to parallelize on conventional data-parallel accelerators such as GPUs, as they typically exhibit less-structured data access patterns and difficult-to-predict dynamic parallelism. This project aims to develop a synergistic design automation framework where a set of novel programming abstractions, architectural templates, synthesis optimization algorithms, and hardware prototypes all play concerted roles to overcome the many challenges raised by the irregular programs. Specifically, the key idea is to automatically generate softly synthesized accelerators that are capable of decoupling data access from computation for tolerating memory latency and performing run-time optimizations for exploiting the irregular parallelism.

该职业研究项目旨在显着提高异构计算机体系结构的设计生产力和质量，该体系结构广泛集成了专用硬件加速器，以继续提供对我们社会各个方面至关重要的计算改进。实现这一目标需要开发一种新的真正集成的设计自动化方法和工具，以实现高效的建模，探索和从高级程序生成硬件加速器，特别是对于新兴应用领域常见的不规则程序，如计算机视觉，机器学习，物理仿真和社交网络分析。该项目还制定了一个广泛但主题集中的教育推广计划，旨在培养下一代工程师和科学家，他们可以弥合软件和硬件设计范式之间的鸿沟。PI将为代表性不足的少数民族高中生领导动手设计课程，并为一年级本科生组织工程研讨会，以增加他们对计算机工程的兴趣和参与。此外，PI将积极将研究成果整合到本科和研究生课程开发中，并利用行业合作有效地向更广泛的受众传播异构计算的研究成果。技术扩展的好处越来越少，导致人们对异构加速器丰富的系统架构越来越感兴趣，以提高在严格的功耗和能源效率限制下的性能。不规则程序在许多重要的应用领域越来越突出;但这些程序在传统的数据并行加速器（如GPU）上并行化要困难得多，因为它们通常表现出结构化较少的数据访问模式和难以预测的动态并行性。该项目旨在开发一个协同设计自动化框架，其中一组新颖的编程抽象，架构模板，合成优化算法和硬件原型都发挥协调一致的作用，以克服不规则程序所带来的许多挑战。具体而言，关键思想是自动生成软合成加速器，能够将数据访问与计算解耦，以容忍内存延迟，并执行运行时优化，以利用不规则的并行性。

项目成果

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs

• DOI: 10.1145/3174243.3174255
• 发表时间: 2018-02
• 期刊: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
• 作者: Yuan Zhou;Udit Gupta;Steve Dai;Ritchie Zhao;Nitish Kumar Srivastava;Hanchen Jin;Joseph Featherston;Yi-Hsiang Lai;Gai Liu;Gustavo Angarita Velasquez;Wenping Wang;Zhiru Zhang

Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations

• DOI: 10.1109/hpca47549.2020.00062
• 发表时间: 2020-02
• 期刊: 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)
• 作者: Nitish Srivastava;Hanchen Jin;Shaden Smith;Hongbo Rong;D. Albonesi;Zhiru Zhang

A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation

• DOI: 10.1145/3174243.3174268
• 发表时间: 2018-02
• 期刊: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
• 作者: Steve Dai;Gai Liu;Zhiru Zhang

Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning

通过专门的冲突驱动学习提高精确模调度的可扩展性

• DOI: 10.1145/3316781.3317842
• 发表时间: 2019
• 期刊: The 56th Annual Design Automation Conference (DAC
• 作者: Dai, Steve;Zhang, Zhiru
• 通讯作者: Zhang, Zhiru

GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs

• DOI: 10.1109/iccad51958.2021.9643582
• 发表时间: 2021-11
• 期刊: 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
• 作者: Yuwei Hu;Yixiao Du;Ecenur Ustun;Zhiru Zhang