CAREER: Synthesizing Highly Efficient Hardware Accelerators for Irregular Programs: A Synergistic Approach

这一职业研究项目旨在显著提高异类计算机体系结构的设计效率和质量，该体系结构广泛集成了专门的硬件加速器，以继续提供对我们社会的各个方面至关重要的计算改进。要实现这一目标，需要开发一种新的真正集成的设计自动化方法和工具，以支持从高级程序进行高效的建模、探索和生成硬件加速器，特别是对于计算机视觉、机器学习、物理模拟和社交网络分析等新兴应用领域中常见的非常规程序。该项目还制定了广泛而有主题的教育推广计划，旨在培养能够弥合软件和硬件设计范例之间鸿沟的下一代工程师和科学家。国际学生联合会将为代表不足的少数族裔高中生主持实践设计课程，并为一年级本科生组织工程研讨会和引人入胜的演示，以提高他们对计算机工程的兴趣和参与。此外，PI将积极将研究成果整合到本科生和研究生课程开发中，并利用行业合作有效地向更广泛的受众传播关于异质计算的研究成果。技术扩展的有限好处导致人们对异质加速器丰富的系统架构越来越感兴趣，以在紧张的功率和能效限制下提高性能。不规则程序在许多重要的应用领域中越来越突出；但这些程序在传统的数据并行加速器(如GPU)上并行化要困难得多，因为它们通常表现出较少结构化的数据访问模式和难以预测的动态并行性。该项目旨在开发一个协同设计自动化框架，在该框架中，一组新颖的编程抽象、体系结构模板、综合优化算法和硬件原型都发挥着协同作用，以克服不规则程序带来的许多挑战。具体地说，关键思想是自动生成软合成加速器，该加速器能够将数据访问与计算解耦以容忍存储器延迟并执行运行时优化以利用不规则并行性。

This CAREER research project aims to significantly improve the design productivity and quality of heterogeneous computer architectures, which extensively integrate specialized hardware accelerators to continue to provide the computing improvements essential to all aspects of our society. Achieving this goal requires the development of a new class of truly integrated design automation methodologies and tools to enable productive modeling, exploration, and generation of hardware accelerators from high-level programs, especially for the irregular programs that are commonplace in emerging application domains such as computer vision, machine learning, physical simulation, and social network analytics. The project also has a broad yet thematically focused plan for educational outreach, which aims to cultivate the next generation of engineers and scientists who can bridge the chasm between the software and hardware design paradigms. The PI will lead hands-on design sessions for underrepresented minority high school students and organize engineering seminars with engaging demonstrations for first-year undergraduates to increase their interest and participation in computer engineering. In addition, the PI will actively integrate the research outcomes into undergraduate and graduate curriculum development, and leverage industrial collaborations to effectively disseminate the research results on heterogeneous computing to a broader audience.Diminished benefits of technology scaling have led to a growing interest in heterogeneous accelerator-rich system architectures to improve performance under tight power and energy efficiency constraints. Irregular programs are gaining prominence in many important application domains; but these programs are much more difficult to parallelize on conventional data-parallel accelerators such as GPUs, as they typically exhibit less-structured data access patterns and difficult-to-predict dynamic parallelism. This project aims to develop a synergistic design automation framework where a set of novel programming abstractions, architectural templates, synthesis optimization algorithms, and hardware prototypes all play concerted roles to overcome the many challenges raised by the irregular programs. Specifically, the key idea is to automatically generate softly synthesized accelerators that are capable of decoupling data access from computation for tolerating memory latency and performing run-time optimizations for exploiting the irregular parallelism.