SHF: Small: Architectural Synthesis for Programmable Accelerators

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Targeted acceleration of functionality in hardware has shown great promise to bring in orders of magnitude improvement in computational capability for a broad range of applications such as artificial intelligence, autonomous vehicles, web search, and virtual reality. However, it is incredibly time consuming and costly to manually design a hardware accelerator that is both high performance and easily programmable for software. This project aims to develop new design automation framework that can automatically generate a high-quality programmable accelerator from architecture specifications defined in a software program. This project builds on the recent advances in high-level synthesis, which is capable of compiling un-timed behavioral specifications into cycle-accurate register-transfer-level circuits. In contrast to conventional high-level synthesis approaches, the proposed framework generates domain-specific instruction-programmable accelerators as opposed to application-specific fixed-function hardware. This research provides a new class of hardware synthesis infrastructure that integrates domain-specific languages, combinatorial optimization algorithms, and data-driven machine learning capabilities to achieve high quality of results on par with those produced by human experts.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.