CAPA: Collaborative Research: A Multi-Paradigm Programming Infrastructure for Heterogeneous Architectures

异构计算与硬件加速器，如FPGA和GPU的广泛使用，已经显示出巨大的希望，带来了数量级的计算效率的提高，为广泛的应用。然而，这种异构平台很难编程，特别是使用FPGA，限制了它们的使用，只有一小部分具有专业硬件知识的程序员。 这项研究的智力价值是开发一个高生产力的多范式编程基础设施的异构体系结构，集成了方便的异构编程模型，自动编译高层次的特定领域的语言，新颖的运行时，和调试支持。该项目更广泛的意义和重要性是将最新的研究引入到多个研究生和本科生课程以及主要会议的教程中，目标是培养新一代多样化的学生和专业人士使用异构编程模型。这些程序员将能够有效地将开发的基础设施应用于我们社会中许多重要的计算密集型应用程序，以进一步推动数字革命。 具体而言，该项目有四个创新研究组成部分：（1）一种名为HeteroCL的新的编程模型，其使得能够在单个统一程序中对异构系统进行编程，（2）一种用于有效地将高级DSL转换为HeteroCL的可重用方法，（3）一种支持HeteroCL编程模型和高级DSL的有效运行时系统，具有将工作负载动态和智能地协同调度到计算层次结构的多个级别的CPU和加速器的独特能力，以及（4）用于仪器化和性能监控的新颖的FPGA性能调试工具。

Heterogeneous computing with extensive use of hardware accelerators, such as FPGAs and GPUs, has shown great promise to bring in orders of magnitude improvement in computing efficiency for a wide range of applications. However, such heterogeneous platforms are difficult to program, especially with FPGAs, limiting their use to only a small subset of programmers with specialized hardware knowledge. The intellectual merits of this research are to develop a highly productive multi-paradigm programming infrastructure for heterogeneous architectures that integrates convenient heterogeneous programming models, automated compilation for high-level domain-specific languages, novel runtime, and debugging support. The project's broader significance and importance are to introduce the latest research into multiple graduate and undergraduate courses and tutorials at major conferences, with the goal of training a new generation of diverse students and professionals to use heterogeneous programming models. These programmers will be able to apply the developed infrastructure effectively to many important compute-intensive applications in our society to further the digital revolution. Specifically, the project has four innovative research components: (1) a new programming model, named HeteroCL, that enables programming of heterogeneous systems in a single unified program, (2) a reusable methodology to efficiently transform high-level DSLs to HeteroCL, (3) an efficient runtime system that support the HeteroCL programming model and high-level DSLs, with unique capability of dynamic and intelligent co-scheduling of workloads to CPUs and accelerators at multiple levels of computing hierarchy, and (4) novel FPGA performance debugging tools for instrumentation and performance monitoring.