Mitigation of Thermal Resistance in High Power Photodiodes as a Means to Increase Device Performance

题目：纳米级界面传热工程以提高高功率光电二极管器件的性能非技术性：模拟光链路正被部署在越来越多的应用中。例子包括有线电视、相控阵天线的波束形成网络、雷达的“天线遥控”，以及世界上最大的射电望远镜之一——智利的阿塔卡马大型毫米/亚毫米阵列射电望远镜的本地振荡器分布。这些模拟链路可以被视为传统电缆或波导的替代品，由于它们的高损耗和有限的带宽，这些电缆或波导通常是不切实际的。高功率、高线性度光电二极管是这些光链路的基本组件，因为它们可以实现高链路增益、低噪声系数和高无杂散动态范围。然而，效率和输出功率受到热失效的强烈限制。热失效通常通过将器件封装在高导热亚基板/基板上来解决。虽然这种方法通常会导致器件输出的增益，但必须减轻光电二极管层和接口中的额外热阻源，以进一步提高器件的效率。这介绍了本提案的总体主题：量化高功率光电二极管每层和界面的热阻，并使用该信息做出明智的设计选择，适用于大型高功率器件，这将导致器件性能的提高。从“热优先”的材料设计和加工前景出发，提高高功率器件的性能，其深远的社会意义将为所有电子器件带来新的材料解决方案和工艺，以减轻建筑设计过程中纳米级的热传输，这将通过更好地使用便携式电源和减少插头负载，从而通过更高效的电子设备减少浪费的能源。此外，这项提议的工作将整合到各种协调的外展活动中，这些活动的重点是通过NanoDays计划增加K-12教室的科学学习和实践活动，在大学实验室进行高中教师和学生的暑期研究，以及会议组织和出席，特别关注弗吉尼亚州周围代表性不足的群体和低收入学校。技术：本提案的首要技术主题是量化改进的单行载流子光电二极管的每层和界面的热阻，并使用该信息做出明智的材料设计选择，适用于大类别的高功率器件。这项工作将通过对器件制造过程中材料选择和加工的假设驱动研究来测量和量化工艺/热性能关系，从而通过逐层热分析确定可行的热缓解途径。该研究基于以下假设：通过精心选择材料、设计接口和加工条件，可以确定并减少大功率器件中的热阻来源，从而大幅提高器件性能。因此，在测试器件级薄膜和薄膜/衬底界面的热性能时，本项目还将推进对键合薄膜和金属/非金属界面中电子和声子输运的理解，特别是关注器件级结构和缺陷，微观结构和加工条件的作用。利用时域热反射进行的纳米级热输运测量，将设计并测试一种新的设备，该设备将重新定义高频光电二极管的功率输出状态。在这种特定的光电二极管中实现的功率增益将指导整个高功率器件的选择，并为材料和加工选择设定标准。该方法将创造新颖、可行的材料解决方案，以更好地理解键合层、键合界面和亚安装接触层中的纳米级电子和声子热输运，从而提高器件性能，这将直接转化为改进的单行载流子光电二极管的记录输出功率。

Title: Nanoscale interfacial heat transfer engineering to increase high power photodiode device performanceNon-technical: Analog optical links are being deployed in a growing number of applications. Examples include cable television, beam-forming networks for phased array antennas, "antenna remoting" for radar, and local oscillator distribution for radio telescopes such as the Atacama large millimeter/sub-millimeter array in Chile, one of the largest radio telescopes in the world. These analog links can be viewed as replacements for conventional electrical cables or waveguides, which are often impractical due to their high loss and limited bandwidth. High-power, high linearity photodiodes are essential components for these optical links since they can enable high link gain, low noise figure, and high spurious free dynamic range. However, the efficiency and output power of strongly limited by thermal failure. Thermal failure is commonly addressed by packaging the devices on high thermal conductivity submounts/substrates. While this approach often leads to gains in device output, there are additional sources of thermal resistance in the photodiode layers and interfaces must be mitigated to further increase the efficiency of devices. This introduces the overarching theme of this proposal: quantifying the thermal resistance at each layer and interface of a high-power photodiode, and using that information to make informed design choices, applicable to a large class of high power devices, that will lead to improved device performance. The far reaching societal implications from improving high power device performance from a "thermal first" material design and processing prospective will lead to novel material solutions and processes for all electronic devices to mitigate thermal transport from the nanoscale level during architecture design, which will lead to reduction of wasted energy via more efficient electronics via better usage of portable power and reduction in plug loads. Furthermore, this proposed work will be integrated into various coordinated outreach activities, which are focused on increasing science learning and hands-on activities in K-12 classrooms through the NanoDays program, high school teacher and student summer research in University Labs and conference organization and attendance, with particular focus on under-represented groups and low-income schools around Virginia. Technical: The overarching technical theme of this proposal is to quantify the thermal resistance at each layer and interface of a modified uni-traveling carrier photodiode, and use that information to make informed material design choices, applicable to a large class of high power devices. This work will measure and quantify the process/thermal property relationships using a hypothesis-driven study of material choice and processing during device fabrication to identify feasible routes for thermal mitigation via layer-by-layer thermal analysis. The research is driven by the following hypothesis: the sources of thermal resistance in high-power devices can be determined and reduced to dramatically increase device performance through careful choice of materials, design of interfaces, and processing conditions. Therefore, in testing thermal properties of device-grade thin films and film/substrate interfaces, this project will also advance the understanding of electron and phonon transport in bonded films and metal/non-metal interfaces, with particular focus on device-level structures and the role of defects, microstructure and processing conditions. From the proposed nanoscale thermal transport measurements conducted with time-domain thermoreflectance, a new device will be designed and tested that will redefine the state of the art power output for high frequency photodiodes. The power gain realized in this specific photodiode will guide the choices for an entire class of high power devices and set the standard for material and processing choices. The approach will create novel, feasible material solutions to improve device performance based on a better understanding of nanoscale electron and phonon thermal transport in the bonding layers, bonded interface and sub-mount contact layers, which will directly translate to record output powers in modified uni-traveling carrier photodiodes.