High Performance Polar Decoders: Algorithm and Hardware Implementation

点击翻译按钮获取中文摘要

Error correction codes provide data reliability against possible errors, and hence are essential to all digital storage and communication systems. Polar codes, a recent breakthrough in the theory of error correction codes, are the first practical error correction codes that are asymptotically optimal in the sense of channel capacity. Their asymptotically optimal performance and low error floor make them promising candidates for future storage and communication systems. However, existing polar decoders suffer from inferior finite length error performance, long decoding delay, and inefficient hardware implementations. These issues form important obstacles to the adoption of polar codes in practice. Jointly addressing these interplaying challenges, the proposed research is a comprehensive investigation of polar decoders from the perspectives of error performance, complexity, delay, and hardware implementation, based on an integrated framework that harnesses the intricate relation between algorithms, their complexities and delays, and their hardware implementations.The proposed research aims to devise new polar decoders that not only achieve superior error performance but also have reduced delay, low complexities, and efficient hardware implementations. To this end, the objectives of the proposed research include: 1) New decoding algorithms for polar codes with improved performance and reduced complexity and delay; 2) Efficient architectures and hardware implementations of polar decoders; 3) Analytical, numerical and experimental performance evaluation of the proposed polar decoders, including a field-programmable gate array emulation platform. The proposed research tackles several key open research problems, such as error performance analysis of symbol-decision polar decoders, how to optimize the schedule of belief propagation decoding of polar codes, and belief propagation decoding of polar codes on over-complete factor graphs. The proposed research also will analytically characterize the error performance of symbol-decision polar decoders, thereby providing theoretical foundations for their future applications. The proposed field-programmable gate array emulation platform not only provides fast performance evaluation of proposed polar decoders, but also facilitates the selection of the appropriate values for various tradeoff parameters.The proposed research is transformative in both theory and practice. The proposed polar decoding algorithms as well as error performance analysis enrich the theory of error correction codes. The proposed decoders for polar codes will lead to better error performance, and have reduced decoding delay and efficient hardware implementations. These factors enable the adoption of polar codes to a wide variety of storage and communication systems, such as digital television, Ethernet, home networking, and Wi-Fi. The integrated design methodology, techniques, and results of the proposed research can be extrapolated to the implementation of other advanced algorithms, and hence impact a wide range of communication and signal processing systems. The integrated education program strengthens and diversifies the science and engineering workforce, and also bridges the gap between advanced signal processing algorithms and their efficient implementations, thus helping to maintain the nation's technological advantage.