High Performance Polar Decoders: Algorithm and Hardware Implementation

高性能 Polar 解码器：算法和硬件实现

• 批准号: 1509674
• 负责人: Zhiyuan Yan
• 金额: $ 30万
• 依托单位: Lehigh University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-08-01 至 2020-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1509674&HistoricalAwards=false
• 关键词: Performance; Polar; Decoders; Algorithm; Hardware

Error correction codes provide data reliability against possible errors, and hence are essential to all digital storage and communication systems. Polar codes, a recent breakthrough in the theory of error correction codes, are the first practical error correction codes that are asymptotically optimal in the sense of channel capacity. Their asymptotically optimal performance and low error floor make them promising candidates for future storage and communication systems. However, existing polar decoders suffer from inferior finite length error performance, long decoding delay, and inefficient hardware implementations. These issues form important obstacles to the adoption of polar codes in practice. Jointly addressing these interplaying challenges, the proposed research is a comprehensive investigation of polar decoders from the perspectives of error performance, complexity, delay, and hardware implementation, based on an integrated framework that harnesses the intricate relation between algorithms, their complexities and delays, and their hardware implementations.The proposed research aims to devise new polar decoders that not only achieve superior error performance but also have reduced delay, low complexities, and efficient hardware implementations. To this end, the objectives of the proposed research include: 1) New decoding algorithms for polar codes with improved performance and reduced complexity and delay; 2) Efficient architectures and hardware implementations of polar decoders; 3) Analytical, numerical and experimental performance evaluation of the proposed polar decoders, including a field-programmable gate array emulation platform. The proposed research tackles several key open research problems, such as error performance analysis of symbol-decision polar decoders, how to optimize the schedule of belief propagation decoding of polar codes, and belief propagation decoding of polar codes on over-complete factor graphs. The proposed research also will analytically characterize the error performance of symbol-decision polar decoders, thereby providing theoretical foundations for their future applications. The proposed field-programmable gate array emulation platform not only provides fast performance evaluation of proposed polar decoders, but also facilitates the selection of the appropriate values for various tradeoff parameters.The proposed research is transformative in both theory and practice. The proposed polar decoding algorithms as well as error performance analysis enrich the theory of error correction codes. The proposed decoders for polar codes will lead to better error performance, and have reduced decoding delay and efficient hardware implementations. These factors enable the adoption of polar codes to a wide variety of storage and communication systems, such as digital television, Ethernet, home networking, and Wi-Fi. The integrated design methodology, techniques, and results of the proposed research can be extrapolated to the implementation of other advanced algorithms, and hence impact a wide range of communication and signal processing systems. The integrated education program strengthens and diversifies the science and engineering workforce, and also bridges the gap between advanced signal processing algorithms and their efficient implementations, thus helping to maintain the nation's technological advantage.

纠错码提供数据可靠性，防止可能出现的错误，因此对于所有数字存储和通信系统至关重要。极性码是纠错码理论的最新突破，是第一个在信道容量意义上渐近最优的实用纠错码。它们的渐近最优性能和低错误底限使它们成为未来存储和通信系统的有希望的候选者。然而，现有的极性解码器存在有限长度错误性能差、解码延迟长和硬件实现效率低的问题。这些问题对Polar码在实践中的采用构成了重要障碍。为了共同解决这些相互影响的挑战，本研究基于一个综合框架，从错误性能、复杂性、延迟和硬件实现的角度对极性解码器进行了全面研究，该框架利用了算法、算法复杂性和延迟及其硬件实现之间的复杂关系。本研究旨在设计新的极性解码器，不仅能实现优异的错误性能，而且还能减少延迟、降低复杂性和提高性能。 高效的硬件实现。为此，本研究的目标包括： 1）新的极性码解码算法，提高性能并降低复杂度和延迟； 2）Polar解码器的高效架构和硬件实现； 3）对所提出的极性解码器进行分析、数值和实验性能评估，包括现场可编程门阵列仿真平台。所提出的研究解决了几个关键的开放研究问题，例如符号决策极性解码器的错误性能分析、如何优化极性码的置信传播解码的调度以及超完备因子图上极性码的置信传播解码。所提出的研究还将分析表征符号决策极性解码器的错误性能，从而为其未来的应用提供理论基础。所提出的现场可编程门阵列仿真平台不仅提供了所提出的极性解码器的快速性能评估，而且还有助于为各种权衡参数选择适当的值。所提出的研究在理论和实践上都是变革性的。所提出的极化解码算法以及错误性能分析丰富了纠错码的理论。所提出的极性码解码器将带来更好的错误性能，并减少解码延迟和高效的硬件实现。这些因素使得 Polar 码得以在各种存储和通信系统中采用，例如数字电视、以太网、家庭网络和 Wi-Fi。所提出的研究的集成设计方法、技术和结果可以外推到其他高级算法的实现，从而影响广泛的通信和信号处理系统。综合教育计划增强了科学和工程劳动力并使之多样化，并弥合了先进信号处理算法与其有效实施之间的差距，从而有助于保持国家的技术优势。