High Performance Polar Decoders: Algorithm and Hardware Implementation

纠错码提供数据可靠性，防止可能的错误，因此是必不可少的所有数字存储和通信系统。极化码是纠错码理论中的一个新突破，是第一种在信道容量意义上渐近最优的实用纠错码。它们的渐近最优性能和低错误平层使它们成为未来存储和通信系统的有希望的候选者。然而，现有的极化解码器遭受较差的有限长度误差性能、长解码延迟和低效的硬件实现。这些问题构成了在实践中采用极化码的重要障碍。为了共同应对这些相互影响的挑战，拟议的研究是从错误性能，复杂性，延迟和硬件实现的角度对极化解码器进行全面调查，基于一个综合框架，该框架利用了算法之间的复杂关系，其复杂性和延迟，以及它们的硬件实现。所提出的研究旨在设计新的极化解码器，其不仅实现上级错误性能而且具有减少的延迟，低复杂度和高效的硬件实现。为此，所提出的研究的目标包括：1）具有改进的性能和降低的复杂度和延迟的极化码的新解码算法; 2）极化解码器的高效架构和硬件实现; 3）所提出的极化解码器的分析、数值和实验性能评估，包括现场可编程门阵列仿真平台。拟议的研究解决了几个关键的开放研究问题，例如符号判决极化解码器的错误性能分析、如何优化极化码的置信传播解码调度以及过完备因子图上极化码的置信传播解码。本文的研究也将为符号判决极化译码器的误码性能分析提供理论依据。所提出的现场可编程门阵列仿真平台不仅提供了快速的性能评估建议的极化解码器，而且还有助于选择合适的值为各种权衡参数，所提出的研究是变革性的理论和实践。本文提出的极化码译码算法及其误码性能分析丰富了纠错码理论。所提出的用于极化码的解码器将导致更好的错误性能，并且具有减少的解码延迟和高效的硬件实现。这些因素使得极化码能够被广泛应用于各种存储和通信系统，例如数字电视、以太网、家庭网络和Wi-Fi。所提出的研究的集成设计方法、技术和结果可以外推到其他先进算法的实现，从而影响广泛的通信和信号处理系统。综合教育计划加强和多样化的科学和工程劳动力，也弥合了先进的信号处理算法及其有效实施之间的差距，从而有助于保持国家的技术优势。

Error correction codes provide data reliability against possible errors, and hence are essential to all digital storage and communication systems. Polar codes, a recent breakthrough in the theory of error correction codes, are the first practical error correction codes that are asymptotically optimal in the sense of channel capacity. Their asymptotically optimal performance and low error floor make them promising candidates for future storage and communication systems. However, existing polar decoders suffer from inferior finite length error performance, long decoding delay, and inefficient hardware implementations. These issues form important obstacles to the adoption of polar codes in practice. Jointly addressing these interplaying challenges, the proposed research is a comprehensive investigation of polar decoders from the perspectives of error performance, complexity, delay, and hardware implementation, based on an integrated framework that harnesses the intricate relation between algorithms, their complexities and delays, and their hardware implementations.The proposed research aims to devise new polar decoders that not only achieve superior error performance but also have reduced delay, low complexities, and efficient hardware implementations. To this end, the objectives of the proposed research include: 1) New decoding algorithms for polar codes with improved performance and reduced complexity and delay; 2) Efficient architectures and hardware implementations of polar decoders; 3) Analytical, numerical and experimental performance evaluation of the proposed polar decoders, including a field-programmable gate array emulation platform. The proposed research tackles several key open research problems, such as error performance analysis of symbol-decision polar decoders, how to optimize the schedule of belief propagation decoding of polar codes, and belief propagation decoding of polar codes on over-complete factor graphs. The proposed research also will analytically characterize the error performance of symbol-decision polar decoders, thereby providing theoretical foundations for their future applications. The proposed field-programmable gate array emulation platform not only provides fast performance evaluation of proposed polar decoders, but also facilitates the selection of the appropriate values for various tradeoff parameters.The proposed research is transformative in both theory and practice. The proposed polar decoding algorithms as well as error performance analysis enrich the theory of error correction codes. The proposed decoders for polar codes will lead to better error performance, and have reduced decoding delay and efficient hardware implementations. These factors enable the adoption of polar codes to a wide variety of storage and communication systems, such as digital television, Ethernet, home networking, and Wi-Fi. The integrated design methodology, techniques, and results of the proposed research can be extrapolated to the implementation of other advanced algorithms, and hence impact a wide range of communication and signal processing systems. The integrated education program strengthens and diversifies the science and engineering workforce, and also bridges the gap between advanced signal processing algorithms and their efficient implementations, thus helping to maintain the nation's technological advantage.