SHF: Medium: Collaborative Research: Atomic scale to circuit modeling of emerging nanoelectronic devices and adapting them to SPICE simulation package

通过利用纳米科学和纳米技术的突破性发现，CMOS技术的积极扩展和随之而来的纳米级新兴技术的发明推动了21世纪计算机、信息、通信和消费电子行业的发展。作为价值数十亿美元的半导体产业的主力，由于在纳米尺度上存在强大的量子力学效应，CMOS技术正接近其规模极限。为了维持后cmos时代经济增长的加速步伐，这项多大学合作研究计划设想以两种重要方式构建VLSI技术的路线图。首先，通过利用非电荷自由度、电子自旋控制磁化、超材料结构中电磁波与半导体之间的相互作用以及拓扑绝缘体中的拓扑状态，将量子输运原理扩展到模拟基于新型半导体和二维层状材料的新兴纳米器件。其次，该研究将通过开发工业级spice兼容的异构电路紧凑型模型，系统地将这些特性从基本的原子限制扩展到电路级集成，这将定义超越摩尔？Law VLSI系统。这项合作提案设想的综合教育、培训和推广活动将包括K-12、本科生、研究生、女性、少数民族和博士后，通过利用参与大学现有的推广活动，在更广泛的社会领域推进科学和工程教育。利用密度泛函理论（DFT）、时变密度泛函理论（TD-DFT）、时变密度矩阵泛函理论（TD-DMFT），对有效质量进行现象学扩展，结合非平衡格林？随着函数（NEGF）方法、量子场论和时域有限差分（FDTD）方法的发展，各种各样的计算方法将被开发出来，以解决未来VLSI系统中多尺度电路的建模问题。由该研究活动产生的软件包和多尺度建模工具将为计算机芯片设计师和制造商提供模拟复杂混合衬底的能力，包括纳米级电子、自旋电子、光电和等离子体器件。最终的软件将被编写，以使来自大学的研究人员和工业中的实践工程师能够开发他们自己的模块，这些模块将产生改进的系统功能、集成密度和操作速度。

Aggressive scaling of CMOS technology and concomitant inventions of nanoscale nascent technologies have fueled the growth of computer, information, communication and consumer electronics industries of the 21st Century by leveraging the ground-breaking discoveries in nanoscience and nanotechnology. The workhorse of multibillion-dollar semiconductor industry, the CMOS technology is approaching its scaling limit due to the strong quantum-mechanical effects present at the nanoscale. To sustain the accelerated pace of economic growth during the post-CMOS era, this multi-university collaborative research proposal envisages building the roadmap of VLSI technology in two significant ways. First, the research is mooted to extend quantum transport principles to simulate emerging nano-devices based on novel semiconductor and 2-D layered materials by exploiting non-charge based degrees of freedom, electron spin controlled magnetization, interaction between electromagnetic waves and semiconductors in metamaterial structures, and topological states in topological insulators. Second, the research will systematically scale these properties from their fundamental atomistic limits to circuit level integration by developing industry-graded SPICE-compatible compact models for heterogeneous circuits that will define the landscape of beyond Moore?s Law VLSI systems. Integrative education, training, and outreach activities envisioned in this collaborative proposal will encompass K-12, undergraduate, graduate, female, minority, and postdoctoral fellows by leveraging the existing outreach activities of participating universities in order to advance science and engineering education in broader segments of the society.Using density-functional theory (DFT), time-dependent density functional theory (TD-DFT), time-dependent density-matrix functional theory (TD-DMFT), to phenomenological Extended Huckel to effective mass, in conjunction with non-equilibrium Green?s function (NEGF) methods, quantum field theory, and finite-difference time domain (FDTD) methods, a wide variety of computational methods are going to be developed to tackle the modeling of multiscale circuits in future VLSI systems. The software packages and multiscale modeling tools resulting from the proposed research activity are going to provide computer chip designers and manufacturers the ability to model complex hybrid substrates comprising nanoscale electronic, spintronic, opto-electronic, and plasmonic devices. The resulting software is going to be written with a view to enabling researchers from universities and practicing engineers in industries to develop their own modules that will engender improved system functionality, integration density, and operational speed.