Low-power Neuromorphic Chip Architecture with in situ Deep Learning

随着超低功耗传感设备被广泛应用于无所不在的无线计算和消费电子产品中，这些产品对我们的日常生活产生了深远的影响，从这些无处不在的传感器中不断积累着大量的数据。为了有效地利用这些数据来提升特定于应用程序的目标，这些传感器平台需要内置智能来实现从传统的基于规则的计算范式到新兴的数据驱动计算方法的过渡。多层神经元网络上的深度学习提供了这样一个机会，通过从传感设备收集的丰富数据中学习来实现智能计算。如何使目前主要运行在通用中央处理器（cpu）和图形处理器（gpu）集群上的能源密集型深度学习适应各种低功耗系统仍然是一个艰巨的挑战。该项目设想发明硬件友好的学习技术，并设计能够实时原位学习的定制低功耗深度学习硬件。创新硬件将在各种低功耗平台上实施，以显著加快新兴物联网（IoT）技术的部署。低功耗深度学习芯片将使能量约束系统能够更智能地感知、处理、组织和利用数据。与收集到的数据相关联的有用信息可以在前端提取和利用，从而减少了系统响应时间和无线通信中的能耗。在这个研究项目中，节能尖峰神经网络（snn）将被用于构建深度学习网络。通过利用图像、音频和视频等多维输入数据的稀疏性，使用事件触发snn可能会显著节省能源。随着CMOS技术的进步，在snn中构建深度神经网络也具有良好的可扩展性。通过地址-事件表示，数百个子snn可以相互连接，以构建大型snn，解决不同类型的大规模问题。在snn中，由于缺乏有效的学习算法而导致的潜在困难将通过制定调制尖峰时间相关的可塑性（STDP）学习规则来解决。通过这些生物启发的在线新学习规则，可以设计基于硬件的snn，用于事件触发计算和深度学习。神经硬件将首先在商用FPGA板上进行原型和验证，然后通过纳米级CMOS技术实现数字化。最后，为了进一步降低超低功耗可穿戴系统的能量耗散，紧急记忆电阻器，即模拟电阻式存储技术将被协集成到CMOS芯片中，以模拟高密度人工突触。可变弹性架构和算法将被开发，以充分利用忆阻器阵列的密度，同时容忍由于几种制造限制而伴随的电导变化。此外，研究和教育的结合将培养包括少数民族和女性在内的未来工程劳动力。在该项目下开发的指导性材料将通过利用NSF支持的nanoHub存储库传播给研究社区和实践工程师。

As ultra-low-power sensing devices are being deployed expansively in all-pervasive wireless computing and consumer electronic products that now profoundly impact our everyday life, enormous amount of data are continuously amassed from these ubiquitous sensors. To exploit these data efficiently for elevating application-specific objectives, built-in intelligences are warranted in these sensor platforms to endow transitions from the traditional rule-based computing paradigm to emerging data-driven computing methods. Deep learning on multi-layered networks of neurons has provided such an opportunity to achieve intelligent computing through learning from the abundant data collected by sensing devices. How to make the current energy-intensive deep learning that mainly runs on clusters of general-purpose central processing units (CPUs) and graphics processing units (GPUs) amenable to various low-power systems remains to be a formidable challenge. This project envisages inventing hardware-friendly learning techniques and designing customized low-power deep learning hardware capable of real-time in-situ learning. The innovative hardware will be implemented on various low-power platforms to significantly accelerate the deployment of the nascent Internet-of-Things (IoT) technology. The low-power deep learning chip will enable energy-constraint systems to sense, process, organize, and utilize the data more intelligently. Useful information associated with the collected data can be extracted and exploited at the front end, thereby reducing the system response time and the energy consumption in wireless communications.In this research project, energy-efficient spiking neural networks (SNNs) will be used to construct deep learning networks. By leveraging the sparsity in multi-dimensional input data such as image, audio and video, the use of event-triggered SNNs can potentially result in significant energy savings. Building deep neural networks in SNNs also has the advantage of good scalability as CMOS technology advances beyond 10 nm. Through address-event representation, hundreds of sub-SNNs can be interconnected to build large SNNs solving disparate types of large-scale problems. Underlying difficulties owing to lack of effective learning algorithms in SNNs will be addressed by formulating the modulated spike-timing-dependent plasticity (STDP) learning rules. Through these bio-inspired on-line new learning rules, hardware-based SNNs can be designed for the event-triggered computation and deep learning. The neural hardware will be at first prototyped and validated on commercial FPGA boards, before realizing digitally by using nano-scale CMOS technology. Finally, in order to further reduce energy dissipation as warranted in ultra-low-power wearable systems, emergent memristor, i.e., analog resistive memory technology will be co-integrated into CMOS chip to mimic high-density artificial synapses. Variation-resilient architectures and algorithms will be developed to fully exploit the density of the memristor arrays, while tolerating their concomitant conductance variations due to several manufacturing limitations. Further, the integration of research and education will train future engineering workforce encompassing minority and female. Instructive materials developed under this project will be disseminated to research communities and practicing engineers by leveraging the NSF supported nanoHub repository.