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SHF: Small: Layout Assessment and Optimization for Disruptive Patterning and Device Technologies

SHF: Small: Layout Assessment and Optimization for Disruptive Patterning and Device Technologies
SHF:小型:颠覆性图案化和器件技术的布局评估和优化
批准号:
1526877
负责人:
Puneet Gupta
金额:
$36.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2015
资助国家:
美国
项目状态:
已结题
起止时间:
2015-06-15 至 2020-05-31

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中文摘要
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英文摘要
Continued scaling of semiconductor technology is essential to preserve the promise of reduced cost, more functional integration and improved performance - all within the same or smaller energy footprint for electronic systems. With integrated circuit fabrication already working at the edge of its physical limits, the semiconductor industry is likely to see several radical changes in the manufacturing and device technologies in the next few years and decades. The broader impact of this proposal lies partly in the artifacts (software, exploration outcome data, etc.) which would enable the academia and industry communities to assess and optimize advanced semiconductor technologies. In addition to enhancing graduate curriculum and engaging undergraduate students in research, the PI will co-organize the Los Angeles Computing Circle: a summer program to expose high school students to non-traditional aspects of computing. On the manufacturing front, the two radical changes that may be seen are (1) use of Extreme Ultraviolet (EUV) light in lithography which has over 10X smaller wavelength than what is used currently with associated improvement in resolution (i.e., potential to shrink transistor and wire dimensions even further); and (2) adoption of Directed Self Assembly (DSA): a scheme where desired patterns self-assemble onto the wafer with some guidance. The other disruption in electronics technology is likely to come from development of vertically oriented transistors (i.e., the current through them flow in z direction instead of x or y) which hold the promise of reduced sleep power, improved performance, smaller area and amenability to integrate heterogeneous materials. The focus of the project is to enable these disruptive technologies that will require substantial changes in design infrastructure and manufacturing-side software tools to be viable. Algorithms and software frameworks for technology development, design layout generation and manufacturability assessment will be developed.
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CAREER: Co-optimization of Integrated Circuit Design and Manufacturing
CPA-DA Collaborative Research: Research on Benchmarking and Robustness of VLSI Sizing Optimizations
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